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12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 evaluation kit available general description the max16065/max16066 flash-configurable system managers monitor and sequence multiple system volt - ages. the max16065/max16066 can also accurately monitor (2.5%) one current channel using a dedicated high-side current-sense amplifier. the max16065 man - ages up to twelve system voltages simultaneously, and the max16066 manages up to eight supply voltages. these devices integrate a selectable differential or sin - gle-ended analog-to-digital converter (adc) and con - figurable outputs for sequencing power supplies. device configuration information, including overvoltage and undervoltage limits, timing settings, and the sequenc - ing order is stored in nonvolatile flash memory. during a fault condition, fault flags and channel voltages can be automatically stored in the nonvolatile flash memory for later read-back. the internal 1% accurate 10-bit adc measures each input and compares the result to one overvoltage, one undervoltage, and one early warning limit that can be configured as either undervoltage or overvoltage. a fault signal asserts when a monitored voltage falls outside the set limits. up to three independent fault output signals are configurable to assert under various fault conditions. because the max16065/max16066 support a power- supply voltage of up to 14v, they can be powered directly from the 12v intermediate bus in many systems. the integrated sequencer provides precise control over the power-up and power-down order of up to twelve (max16065) or up to eight (max16066) power supplies. eight outputs (en_out1?en_out8) are configurable with charge-pump outputs to directly drive external n-channel mosfets. the max16065/max16066 include eight/six programma - ble general-purpose inputs/outputs (gpio_s). gpio_s are flash configurable as dedicated fault outputs, as a watchdog input or output, or as a manual reset. the max16065/max16066 feature nonvolatile fault memory for recording information during system shut - down events. the fault logger records a failure in the internal flash and sets a lock bit protecting the stored fault data from accidental erasure. an smbus or a jtag serial interface configures the max16065/max16066. the max16065 is available in a 48-pin, 7mm x 7mm, tqfn package, and the max16066 is available in a 40-pin, 6mm x 6mm, tqfn package. both devices are fully specified from -40 n c to +85 n c. features s operate from 2.8v to 14v s 2.5% current-monitoring accuracy s 1% accurate 10-bit adc monitors 12/8 voltage inputs s single-ended or differential adc for system voltage/current monitoring s integrated high-side current-sense amplifier s 12/8 monitored inputs with overvoltage/undervoltage/early warning limit s nonvolatile fault event logger s power-up and power-down sequencing capability s independent secondary sequence block s 12/8 outputs for sequencing/power-good indicators s two programmable fault outputs and one reset output s eight general-purpose inputs/outputs configurable as: dedicated fault outputs watchdog timer function manual reset margin enable s smbus (with timeout) or jtag interface s flash configurable time delays and thresholds s -40 n c to +85 n c operating temperature range applications networking equipmenttelecom equipment (base stations, access) storage/raid systems servers 19-4717; rev 4; 3/15 ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. typical operating circuits appear at end of data sheet. part temp range pin-package max16065 etm+ -40 n c to +85 n c 48 tqfn-ep* max16066 etl+ -40 n c to +85 n c 40 tqfn-ep* for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maximintegrated.com. downloaded from: http:///
2 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , csp, csm to gnd ........................................ -0.3v to +15v csp to csm .......................................................... -0.7v to +0.7v mon_, gpio_, scl, sda, a0, reset, en_out9?en_out12 to gnd (programmed as open-drain outputs) ........ -0.3v to +6v en, tck, tms, tdi to gnd .................................... -0.3v to +4v dbp, abp to gnd ...... -0.3v to the lower of +4v or (v cc + 0.3v) en_out1?en_out8 to gnd (programmed as open-drain outputs) ............................................................ -0.3v to +15v tdo, en_out_, gpio_, reset (programmed as push-pull outputs)............................................... -0.3v to (v dbp + 0.3v) input/output current ......................................................... 20ma continuous power dissipation (t a = +70 n c) 40-pin tqfn (derate 26.3mw/ n c above +70 n c) ....... 2105mw 48-pin tqfn (derate 27.8mw/ n c above +70 n c) ....... 2222mw operating temperature range .......................... -40 n c to +85 n c junction temperature .................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v cc = 2.8v to 14v, t a = -40 n c to +85 n c, unless otherwise specified. typical values are at v abp = v dbp = v cc = 3.3v, t a = +25 n c.) (note 1) absolute maximum ratings parameter symbol conditions min typ max units operating voltage range v cc reset output asserted low 1.2 v (note 2) 2.8 14 undervoltage lockout (rising) v uvlo minimum voltage on v cc to ensure the device is flash configurable 2.7 v undervoltage lockout hysteresis v uvlo_hys 100 mv minimum flash operatingvoltage v flash minimum voltage on v cc to ensure flash erase and write operations 2.7 v supply current i cc no load on output pins 4.5 7 ma during flash writing cycle 10 14 abp regulator voltage v abp c abp = 1f, no load, v cc = 5v 2.85 3 3.15 v dbp regulator voltage v dbp c dbp = 1f, no load, v cc = 5v 2.8 3 3.1 v boot time t boot v cc > v uvlo 200 350 s flash writing time 8-byte word 122 ms internal timing accuracy (note 3) -8 +8 % en input voltage v th_en_r en voltage rising 1.41 v v th_en_f en voltage falling 1.365 1.39 1.415 en input current i en -0.5 +0.5 a mon_ input voltage range 0 5.5 v downloaded from: http:///
3 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 electrical characteristics (continued)(v cc = 2.8v to 14v, t a = -40 n c to +85 n c, unless otherwise specified. typical values are at v abp = v dbp = v cc = 3.3v, t a = +25 n c.) (note 1) parameter symbol conditions min typ max units adc dc accuracyresolution 10 bits gain error adc gain t a = +25c 0.35 % t a = -40c to +85c 0.70 offset error adc off 1 lsb integral nonlinearity adc inl 1 lsb differential nonlinearity adc dnl 1 lsb adc total monitoring cycle time t cycle no mon_ fault detected 40 50 s adc in_ ranges 1 lsb = 5.43mv 5.56 v 1 lsb = 2.72mv 2.78 1 lsb = 1.36mv 1.39 current sense csp input-voltage range v csp 3 14 v input bias current i csp 14 25 a i csm v csp = v csm 3 5 csp total unadjusted error csp err (note 4) 2 %fsr overcurrent differential threshold ovc th v csp - v csm gain = 48 21.5 25 30.5 mv gain = 24 46 51 56 gain = 12 94 101 108 gain = 6 190 202 210 v sense fault threshold hysteresis ovc hys 0.5 %ovc th secondary overcurrent threshold timeout ovc del r73h[6:5] = ?00? 0 ms r73h[6:5] = ?01? 3 4 5 r73h[6:5] = ?10? 12 16 20 r73h[6:5] = ?11? 50 64 60 v sense ranges gain = 6 232 mv gain = 12 116 gain = 24 58 gain = 48 29 adc current measurement accuracy v sense = 150mv (gain = 6 only) -2.5 q 0.2 +2.5 % v sense = 50mv, gain = 12 -4 q 0.2 +4 v sense = 25mv, gain = 24 q 0.5 v sense = 10mv, gain = 48 q 1 gain accuracy v sense = 20mv to 100mv, v csp = 5v, gain = 6 -1.5 +1.5 % common-mode rejection ratio cmrr sns v csp > 4v 80 db power-supply rejection ratio psrr sns 80 db downloaded from: http:///
4 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 electrical characteristics (continued)(v cc = 2.8v to 14v, t a = -40 n c to +85 n c, unless otherwise specified. typical values are at v abp = v dbp = v cc = 3.3v, t a = +25 n c.) (note 1) parameter symbol conditions min typ max units outputs (en_out_, reset, gpio_) output-voltage low v ol i sink = 2ma 0.4 v i sink = 10ma, gpio_ only 0.7 v cc = 1.2v, i sink = 100a (reset only) 0.3 maximum output sink current total current into en_out_, reset, gpio_, v cc = 3.3v 30 ma output-voltage high (push-pull) i source = 100a 2.4 v output leakage (open drain) 1 a v en_out1 - v en_out8 = 13.2v 5 out_ overdrive (charge pump) (en_out1?en_out8 only) i gate_ = 1a 10 11 13 v out_ pullup current (charge pump) i ch_up during power up, v gate = 1v 2.5 4 a smbus interface logic-input low voltage v il input voltage falling 0.8 v logic-input high voltage v ih input voltage rising 2.0 v input leakage current in = gnd or v cc -1 +1 a output voltage low (sda/scl) v ol i sink = 3ma 0.4 v input capacitance c in 5 pf smbus timeout t timeout scl time low for reset 25 35 ms inputs (a0, gpio_) input logic-low v il 0.8 v input logic-high v ih 2.0 v wdi pulse width t wdi 100 ns mr pulse width t mr 1 s mr to reset delay 0.5 s mr glitch rejection 100 ns smbus timing serial clock frequency f scl 400 khz bus free time between stop and start condition t buf 1.3 s start condition setup time t su:sta 0.6 s start condition hold time t hd:sta 0.6 s stop condition setup time t su:sto 0.6 s clock low period t low 1.3 s clock high period t high 0.6 s data setup time t su:dat 100 ns downloaded from: http:///
5 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 electrical characteristics (continued) (v cc = 2.8v to 14v, t a = -40 n c to +85 n c, unless otherwise specified. typical values are at v abp = v dbp = v cc = 3.3v, t a = +25 n c.) (note 1) note 1: specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at t a = +25 n c and t a = +85 n c. specifications at t a = -40 n c are guaranteed by design. note 2: for v cc of 3.6v or lower, connect v cc , dbp, and abp together. for higher supply applications, connect only v cc to the supply rail. note 3: applies to reset, fault, autoretry, sequence delays, and watchdog timeout. note 4: total unadjusted error is a combination of gain, offset, and quantization error. parameter symbol conditions min typ max units output fall time t of c bus = 10pf to 400pf 250 ns data hold time t hd:dat from 50% scl falling to sda change 0.3 0.9 s pulse width of spike suppressed t sp 30 ns jtag interfacetdi, tms, tck logic-low input voltage v il input voltage falling 0.8 v tdi, tms, tck logic-high input voltage v ih input voltage rising 2 v tdo logic-output low voltage v ol i sink = 3ma 0.4 v tdo logic-output high voltage v oh i source = 200a 2.4 v tdi, tms pullup resistors r pu pullup to dbp 40 50 60 k i/o capacitance c i/o 5 pf tck clock period t 1 1000 ns tck high/low time t 2 , t 3 50 500 ns tck to tms, tdi setup time t 4 15 ns tck to tms, tdi hold time t 5 10 ns tck to tdo delay t 6 500 ns tck to tdo high-z delay t 7 500 ns downloaded from: http:///
6 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 figure 1. smbus timing diagram figure 2. jtag timing diagram stop condition repeated start condition start condition t high t low t r t f t su:dat t su:sta t su:sto t hd:sta t buf t hd:sta t hd:dat scl sda start condition tck t 1 t 2 t 3 t 4 t 5 t 6 t 7 tdi, tms tdo downloaded from: http:///
7 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 typical operating characteristics (typical values are at v cc = 3.3v, t a = +25c, unless otherwise noted.) mon_ deglitch vs. transient duration max16065 toc06 deglitch value transient duration ( s) 20 40 60 80 100 120 0 2 48 16 transient duration vs. threshold overdrive (en) max16065 toc04 en overdrive (mv) transient duration ( s) 10 20 40 60 80 100 120 140 160 0 1 100 normalized mon_ threshold vs. temperature max16065 toc02 normalized mon_ threshold 60 40 20 0 -20 0.2 0.4 0.6 0.8 1.0 1.2 0 -40 80 temperature ( n c) 5.6v range,half scale, puv threshold normalized en threshold vs. temperature max16065 toc03 temperature ( n c) normalized en threshold 80 60 40 20 0 -20 0.994 0.996 0.998 1.000 1.002 1.004 1.0060.992 -40 v cc supply current vs. v cc supply voltage max16065 toc01 v cc (v) i cc (ma) 12 10 8 6 4 2 1 2 3 4 5 60 01 4 t a = +85 n c t a = +25 n c t a = -40 n c for low-voltage applicationsv cc < 3.6v connect abp and dbp to v cc abp and dbpregulators active abp and dbp connected to v cc normalized timing accuracy vs. temperature max16065 toc05 normalized slot delay 80 60 40 20 0 -20 0.974 0.976 0.978 0.980 0.982 0.984 0.9860.972 -40 temperature ( n c) mr to reset propagation delay vs. temperature max16065 toc07 delay ( s) 80 60 20 40 0 -20 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 -40 temperature ( n c) min max output voltage vs. sink current (out = low) max16065 toc08 i out (ma) v out (v) 15 10 5 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0 02 0 en_out_ reset gpio_ output-voltage high vs. source current (charge-pump output) max16065 toc09 3 2 1 2 4 6 8 10 12 0 04 i out (a) v out (v) downloaded from: http:///
8 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 typical operating characteristics (continued) (typical values are at v cc = 3.3v, t a = +25c, unless otherwise noted.) normalized current-sense accuracy vs. temperature max16065 toc13 temperature ( n c) normalized current-sense output 0.97 0.99 1.01 1.03 1.050.95 25mv 200mv 100mv 60 40 20 0 -20 -40 80 output-voltage high vs. source current (push-pull output) 1000 500 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.42.4 0 1500 max16065 toc10 i out (a) v out (v) reset en_out_ gpio_ integral nonlinearity vs. code max16065 toc11 code (lsb) inl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 differential nonlinearity vs. code max16065 toc12 code (lsb) dnl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 current-sense accuracy vs. csp-csm voltage max16065 toc14 csp-csm voltage (mv) error (mv) 25 20 15 10 5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 03 0 current-sense transient duration vs. csp-csm overdrive max16065 toc15 csp-csm overdrive (mv) transient duration (s) 80 60 40 20 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 0 100 max16065 toc16 20ms/div fet turn-on with charge pump en_out_ i load v load max16065 toc17 20ms/div sequencing mode reset output current vs. supply voltage max16065 toc18 supply voltage (v) output current (ma) 12 10 6 8 4 2 2 4 6 8 10 12 14 16 18 0 01 4 abp and dbp regulators active abp and dbpconnected to v cc v reset = 0.3v downloaded from: http:///
9 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 pin configurations top view max16065 thin qfn (7mm x 7mm) 13 14 15 16 17 18 19 20 21 22 23 24 tdo sda ao scl gnd gpio7 gpio8 gpio1 gpio2 gpio3 gpio4 gpio5 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 + 456789 10 11 12 mon12 mon11 mon10 mon9 mon8 mon7 gnd abp v cc dbp en en_out1 tck tdi tms reset csm csp mon6 mon5 mon4 mon3 mon2 mon1 36 *ep 35 34 33 32 31 30 29 28 27 26 25 gpio6 en_out12 en_out11 en_out10 en_out9 en_out8 en_out7 en_out6 en_out5 en_out4 en_out3 en_out2 top view max16066 thin qfn (6mm x 6mm) 3536 34 33 1211 13 mon3mon5 mon6 csp csm 14 mon2 en_out4en_out6 en_out7 en_out3 en_out2 en_out1en_out8 gpio6 12 abp 45 67 27 28 29 30 26 24 23 22 gnd mon7 gpio2gpio1 gnd scl mon4 en_out5 3 25 37 mon8 ao 3839 40 mon9 mon10 mon1 sdatdo tck v cc 32 15 gpio3 dbp 31 16 17 18 19 20 gpio4 reset tms tdi gpio5 89 10 21 en *ep + downloaded from: http:///
10 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 pin description pin name function max16065 max16066 1?6, 43?46 40, 1?5, 36?39 mon1? mon10 monitor voltage inputs. set monitor voltage range through configuration registers. measured value written to adc register can be read back through the smbus or jtag interface. 47, 48 ? mon11, mon12 monitor voltage inputs. set monitor voltage range through configuration registers. measured value written to adc register can be read back through the smbus or jtag interface. 7 6 csp current-sense amplifier positive input. connect csp to the source side of the external sense resistor. 8 7 csm current-sense amplifier negative input. connect csm to the load side of the external sense resistor. 9 8 reset configurable reset output 10 9 tms jtag test mode select 11 10 tdi jtag test data input 12 11 tck jtag test clock 13 12 tdo jtag test data output 14 13 sda smbus serial-data open-drain input/output 15 14 a0 four-state smbus address. address sampled upon por. 16 15 scl smbus serial-clock input 17, 42 16, 35 gnd ground 20?25 17?22 gpio1? gpio6 general-purpose input/outputs. gpio_s can be configured to act as a ttl input, a push-pull, open-drain, or high-impedance output or a pulldown circuit during a fault event. 18, 19 ? gpio7, gpio8 general-purpose input/outputs. gpio_s can be configured to act as a ttl input, a push-pull, open-drain, or high-impedance output or a pulldown circuit during a fault event or reverse sequencing. 26?29 ? en_out12? en_out9 outputs. set en_out_ with active-high/active-low logic and with push-pull or open-drain configuration. en_out_ can be asserted by a combination of in_ voltages configurable through the flash. 30?37 23?30 en_out8? en_out1 outputs. set en_out_ with active-high/active-low logic and with push-pull or open-drain configuration. en_out_ can be asserted by a combination of in_ voltages configurable through the flash. en_out1?en_out8 can be configured with a charge-pump output (+10v above gnd) that can drive an external n-channel mosfet. 38 31 en analog enable input. all outputs deassert when v en is below the enable threshold. 39 32 dbp digital bypass. all push-pull outputs are referenced to dbp. bypass dbp with a 1 f f capacitor to gnd. 40 33 v cc device power supply. connect v cc to a voltage from 2.8v to 14v. bypass v cc with a 10 f f capacitor to gnd. 41 34 abp analog bypass. bypass abp with a 1 f f ceramic capacitor to gnd. ? ? ep exposed pad. internally connected to gnd. connect to ground, but do not use as the main ground connection. downloaded from: http:///
11 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 functional diagram v cc abp dbp reset g p i oc o n t r o l any_faultfault1 reset gpio1gpio2 gpio3 gpio4gpio5 gpio6 gpio1?gpio8 gpio7gpio8 en_out1 ? en_out12 fault2mr margin wdi watchdog timer decode logic primary sequence block digital comparators adc registers 10-bit adc (sar) voltage scaling and mux ram registers flash memory jtag interface smbus interface ao gnd scl sda tdo tdi tck tms ref v csth 1.4v en csp csm mon1? mon12 a v secondary sequence block wdo overc max16065 downloaded from: http:///
12 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 detailed description the max16065 manages up to twelve system power supplies and the max16066 can manage up to eight system power supplies. after boot-up, if en is high and the software enable bit is set to ?1,? a power-up sequence begins based on the configuration stored in flash and the en_out_s are controlled accordingly. when the power-up sequence is successfully completed, the monitoring phase begins. an internal multiplexer cycles through each mon_ input. at each multiplexer stop, the 10-bit adc converts the monitored analog voltage to a digital result and stores the result in a register. each time a conversion cycle (50 f s, max) completes, internal logic circuitry compares the conversion results to the over - voltage and undervoltage thresholds stored in memory. when a result violates a programmed threshold, the conversion can be configured to generate a fault. gpio_ can be programmed to assert on combinations of faults. additionally, faults can be configured to shut off the sys- tem and trigger the nonvolatile fault logger, which writes all fault information automatically to the flash and write- protects the data to prevent accidental erasure. the max16065/max16066 contain both smbus and jtag serial interfaces for accessing registers and flash. use only one interface at any given time. for more information on how to access the internal memory through these interfaces, see the smbus-compatible interface and jtag serial interface sections. the memory map is divided into three pages with access controlled by special smbus and jtag commands. the factory-default values at por (power-on reset) for all ram registers are ?0?s. por occurs when v cc reach - es the undervoltage-lockout threshold (uvlo) of 2.8v (max). at por, the device begins a boot-up sequence. during the boot-up sequence, all monitored inputs are masked from initiating faults and flash contents are cop - ied to the respective register locations. during boot-up, the max16065/max16066 are not accessible through the serial interface. the boot-up sequence takes up to 350 f s, after which the device is ready for normal operation. reset is asserted low up to the boot-up phase and remains asserted for its programmed timeout period once sequencing is completed and all monitored channels are within their respective thresholds. up to the boot-up phase, the gpio_s and en_out_s are high impedance. power apply 2.8v to 14v to v cc to power the max16065/ max16066. bypass v cc to ground with a 10 f f capacitor. two internal voltage regulators, abp and dbp, supply power to the analog and digital circuitry within the device. for operation at 3.6v or lower, disable the regulators by connecting abp and dbp to v cc . abp is a 3.0v (typ) voltage regulator that powers the internal analog circuitry. bypass abp to gnd with a 1 f f ceramic capacitor installed as close to the device as possible.dbp is an internal 3.0v (typ) voltage regulator. dbp powers flash and digital circuitry. all push-pull outputs refer to dbp. dbp supplies the input voltage to the i nternal charge pump when the programmable outputs are configured as charge-pump outputs. bypass the dbp output to gnd with a 1 f f ceramic capacitor installed as close as possible to the device.do not power external circuitry from abp or dbp. sequencing to sequence a system of power supplies safely, the output voltage of a power supply must be good before the next power supply may turn on. connect en_out_ outputs to the enable input of an external power supply and connect mon_ inputs to the output of the power supply for voltage monitoring. more than one mon_ can be used if the power supply has multiple outputs. sequence order the max16065/max16066 provide a system of ordered slots to sequence multiple power supplies. to determine the sequence order, assign each en_out_ to a slot ranging from slot 1 to slot 12. en_out_(s) assigned to slot 1 are turned on first, followed by outputs assigned to slot 2, and so on through slot 12. multiple en_out_s assigned to the same slot turn on at the same time. each slot includes a built-in configurable sequence delay (registers r77h to r7dh) ranging from 20 f s to 1.6s. during a reverse sequence, slots are turned off in reverse order starting from slot 12. the max16065/max16066 can be configured to power-down in simultaneous mode or in reverse sequence mode as set in r75h[0]. see tables 5 and 6 for the en_out_ slot assignment bits, and tables 3 and 4 for the sequence delays. during power-up or power-down sequencing, the current sequencer state can be found in r21h[4:0]. downloaded from: http:///
13 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 multiple sequencing groups the max16065/max16066 sequencing slots can be split into two groups: the primary sequence and the secondary sequence. the last slot of the primary sequence is selected using register bits r7dh[7:4]. the secondary sequence begins at the slot after the one specified in register bits r7dh[7:4]. the primary sequence is controlled by the en input and the software enable bit in r73h[0]. outputs assigned to slots in the primary sequence turn on, and monitoring begins for inputs assigned to these slots. reset deasserts after the primary sequence and timeout period completes. to initiate secondary sequencing and monitoring, set the software enable r73h[1] bit to 1. additionally, if gpio_ is configured as en2 then both the software enable 2 and en2 must be high. outputs assigned to slots in the secondary sequence turn on, and monitoring begins for inputs assigned to these slots. if a gpio_ is configured as the reset2 output, it deasserts after the secondary sequence and timeout period completes. if a critical fault occurs in the primary sequence group, both sequence groups automatically shut down. if a critical fault occurs in the secondary sequence group, then just the outputs assigned to slots in the second - ary sequence turn off. the failing slot in secondary sequence is stored in r1dh. multiple sequencing groups can be used to conserve power by powering down secondary systems when not in use. enable and enable2 to initiate sequencing/tracking and enable monitoring, the voltage at en must be above 1.4v and the software enable bit in r73h[0] must be set to ?1.? to power down and disable monitoring, either pull en below 1.35v or set the software enable bit to ?0.? see table 2 for the software enable bit configurations. connect en to abp if not used. if a fault condition occurs during the power-up cycle, the en_out_ outputs are powered down immediately, regardless of the state of en. in the monitoring state, if en falls below the threshold, the sequencing state machine begins the power-down sequence. if en rises above the threshold during the power-down sequence, the sequence state machine continues the power-down sequence until all the channels are powered off and then the device immediately begins the power-up sequence. when in the monitoring state, a register bit, enreset, is set to a ?1? when en falls below the undervoltage threshold. this register bit latches and must be cleared through software. this bit indicates if reset asserted low due to en going under the threshold. the por state of enreset is ?0?. the bit is only set on a falling edge table 1. current sequencer slot register address bit range description 21h [4:0] current sequencer state:00000 = slot 0 00001 = slot 1 00010 = slot 2 00011 = slot 3 00100 = slot 4 00101 = slot 5 00110 = slot 6 00111 = slot 7 01000 = slot 8 01001 = slot 9 01010 = slot 10 01011 = slot 11 01100 = slot 12 01101 = secondary sequence monitoring mode 01110 = primary sequence fault 01111 = primary sequence monitoring mode 10000 = secondary sequence fault 10001 to 11111 = reserved [7:5] reserved downloaded from: http:///
14 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 of the en comparator output or the software enable bit. if operating in latch-on fault mode, toggle en or toggle the software enable bit to clear the latch condition and restart the device once the fault condition has been removed. to initiate secondary sequencing and monitoring set the software enable r73h[1] bit to 1. additionally, if gpio_ is configured as en2 then both the software enable 2 bit and en2 must be high. to power-down and disable monitoring, either drive en2 low or set the software enable2 bit to ?0.? see table 2 for the software enable bit configurations. when a fault condition occurs during the power-up cycle, the en_out_ outputs are powered down immediately, independent of the state of en2. drive en2 low to begin the secondary power-down sequence. when en2 is driven high during the power-down sequence, the sequence state machine continues the power-down sequence until the secondary channels are powered off and then the device immediately begins the power-up sequence. monitoring inputs while sequencing an enabled mon_ input can be assigned to a slot ranging from slot 1 to slot 12. en_out_s are always asserted at the beginning of a slot. the supply volt - ages connected to the mon_ inputs must exceed the undervoltage threshold before the programmed timeout period expires otherwise a fault condition will occur. the undervoltage threshold checking cannot be disabled during power-up and power-down. see tables 5 and 6 for the mon_ slot assignment bits. the programmed table 2. software enable configurations table 3. slot delay register register address flash address bit range description 73h 273h [0] software enable 1 (primary sequence) [1] software enable 2 (secondary sequence) [2] 1 = margin mode enabled [3] early warning threshold select0 = early warning is undervoltage 1 = early warning is overvoltage [4] independent watchdog mode enable1 = watchdog timer is independent of sequencer 0 = watchdog timer boots after sequence completes register address flash address bit range description 77h 277h [3:0] sequence slot 0 delay [7:4] sequence slot 1 delay 78h 278h [3:0] sequence slot 2 delay [7:4] sequence slot 3 delay 79h 279h [3:0] sequence slot 4 delay [7:4] sequence slot 5 delay 7ah 27ah [3:0] sequence slot 6 delay [7:4] sequence slot 7 delay 7bh 27bh [3:0] sequence slot 8 delay [7:4] sequence slot 9 delay 7ch 27ch [3:0] sequence slot 10 delay [7:4] sequence slot 11 delay 7dh 27dh [3:0] sequence slot 12 delay [7:4] grouped sequence split location, final slot of primary sequence downloaded from: http:///
15 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 sequence delay is then counted before moving to the next slot. slot 0 does not monitor any mon_ input and does not control any en_out_. slot 0 waits for the software enable bit r73h[0] to be a logic-high and for the voltage on en to rise above 1.4v before initiating the power-up sequence and counting its own sequence delay. any mon_ input that suffers a fault that occurs during power-up sequencing causes all the en_out_s to turn off and the sequencer to shut down regardless of the state of the critical fault enables (see the faults section for more information). if a mon_ input is less critical to system operation, it can be configured as ?monitoring only? (see table 6) for either the primary or secondary sequence. monitoring for mon_ inputs assigned as ?monitoring only? begins after sequencing is complete for that group, and can trigger a critical fault only if specifically configured to do so using the critical fault enables. power-up on power-up, when en is high and the software enable bit is 1, the max16065/max16066 begin sequencing with slot 0. after the sequencing delay for slot 0 expires, the sequencer advances to slot 1, and all en_out_s assigned to the slot assert. all mon_ inputs assigned to slot 1 are monitored and when the voltage rises above the uv fault threshold, the sequence delay counter is started. when the t fault counter expires before all mon_ inputs assigned to the slot are above the fault uv threshold, a fault asserts. en_out_ outputs are disabled and the max16065/max16066 return to the power-off state. when the sequence delay expires, the max16065/ max16066 proceed to the next slot. after the voltages on all mon_ inputs assigned to the last slot exceed the uv fault threshold and the slot delay expires, the max16065/max16066 start the reset time - out counter. after the reset timeout, reset deasserts. r75h[4:1] sets the t fault delay. see table 7 for details. power-down power-down starts when en is pulled low or the software enable bit is set to ?0.? power down en_out_s simultaneously or in reverse-sequence mode by setting the reverse sequence bit (r75h[0]) appropriately. reverse-sequence mode when the max16065/max16066 are fully powered up (including secondary sequence group, if enabled) and en or the software enable bit is set to ?0?, the en_out_s assigned to slot 12 deassert, the max16065/max16066 wait for the slot 12 sequence delay and then proceed to the previous slot (slot 11), and so on until the en_out_s assigned to slot 1 turn off. when simultaneous power- down is selected (r75h[0] set to ?0?), all en_out_s turn off at the same time. table 4. power-up/power-down slot delays code value 0000 25 f s 0001 500 f s 0010 1ms 0011 2ms 0100 3ms 0101 4ms 0110 6ms 0111 8ms 1000 10ms 1001 12ms 1010 25ms 1011 100ms 1100 200ms 1101 400ms 1110 800ms 1111 1.6s downloaded from: http:///
16 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 figure 3. delay and reset timing table 5. mon_ and en_out_ assignment registers register address flash address bit range description 7eh 27eh [3:0] mon1 [7:4] mon2 7fh 27fh [3:0] mon3 [7:4] mon4 80h 280h [3:0] mon5 [7:4] mon6 81h 281h [3:0] mon7 [7:4] mon8 82h 282h [3:0] mon9 [7:4] mon10 83h 283h [3:0] mon11 [7:4] mon12 slot 0 en_out1 both are assigned to slot 1 mon4 en_out2 mon3mon5 reset en slot 1 t fault ov uv slot1-slot0 delay slot0 delay mon4 must reach uv threshold by this time uv/ov monitoring begins when mon4reaches uv threshold slot 2 final slot (primary sequence) reset timeout both are assigned to slot 2 downloaded from: http:///
17 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 5. mon_ and en_out_ assignment registers (continued) table 6. mon_ and en_out_ slot assignment codes register address flash address bit range description 84h 284h [3:0] en_out1 [7:4] en_out2 85h 285h [3:0] en_out3 [7:4] en_out4 86h 286h [3:0] en_out5 [7:4] en_out6 87h 287h [3:0] en_out7 [7:4] en_out8 88h 288h [3:0] en_out9 [7:4] en_out10 89h 289h [3:0] en_out11 [7:4] en_out12 slot assignment code mon_ description en_out_ description 0000 not assigned not assigned 0001 slot 1 slot 1 0010 slot 2 slot 2 0011 slot 3 slot 3 0100 slot 4 slot 4 0101 slot 5 slot 5 0110 slot 6 slot 6 0111 slot 7 slot 7 1000 slot 8 slot 8 1001 slot 9 slot 9 1010 slot 10 slot 10 1011 slot 11 slot 11 1100 slot 12 slot 12 1101 monitoring only, secondary sequence general-purpose input (en_out9?en_out12 only) 1110 monitoring only, primary sequence general-purpose output (en_out9?en_out12 only) 1111 not assigned not assigned downloaded from: http:///
18 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 7. t fault delay settings when the secondary sequence group is already powered down and en or the software enable bit is set to ?0?, the reverse power-down sequence is similar to above, but starts from the last slot assigned to the primary sequence r7dh[7:4]. after the last assigned slot is powered down the previous slot will power down and so on until slot 0 is powered down. to power down the secondary sequence group, drive en2 low or set r75h[1] to ?0?. the secondary reverse power-down sequence will start at slot 12 and end at the primary sequence monitoring mode state at which point only the slots assigned to the primary sequence are active. voltage/current monitoring the max16065/max16066 feature an internal 10-bit adc that monitors the mon_ voltage inputs. an internal multiplexer cycles through each of the enabled inputs, taking less than 40 f s for a complete monitoring cycle. each acquisition takes approximately 3.2 f s. at each multiplexer stop, the 10-bit adc converts the analog input to a digital result and stores the result in a register. adc conversion results are stored in registers r00h to r1ah (see table 10). use the smbus or jtag serial inter - face to read adc conversion results.the max16065 provides twelve inputs, mon1 ? mon12, for voltage monitoring. the max16066 provides eight inputs, mon1 ? mon8, for voltage monitoring. each input voltage range is programmable in registers r43h to r45h (see table 9). when mon_ configuration registers are set to ?11,? mon_ voltages are not monitored, and the multiplexer does not stop at these inputs, decreasing the total cycle time. these inputs cannot be configured to trigger fault conditions. the three programmable thresholds for each monitored voltage include an overvoltage, an undervoltage, and a secondary warning threshold that can be set in r73h[3] to be either an undervoltage or overvoltage threshold. see the faults section for more information on setting overvoltage and undervoltage thresholds. all voltage thresholds are 8 bits wide. the 8 msbs of the 10-bit adc conversion result are compared to these overvoltage and undervoltage thresholds. for any undervoltage or overvoltage condition to be monitored and any faults detected, the mon_ input must be assigned to a sequence order or set to monitoring mode as described in the sequencing section. inputs that are not enabled are not converted by the adc; they contain the last value acquired before that channel was disabled. the adc conversion result registers are reset to 00h at boot-up. these registers are not reset when a reboot command is executed. configure the max16065/max16066 for differen - tial mode in r46h (table 9). the possible differential code delay 0000 120 f s 0001 150 f s 0010 250 f s 0011 380 f s 0100 600 f s 0101 1ms 0110 1.5ms 0111 2.5ms 1000 4ms 1001 6ms 1010 10ms 1011 15ms 1100 25ms 1101 40ms 1110 60ms 1111 100ms downloaded from: http:///
19 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 pairs are mon1/mon2, mon3/mon4, mon5/mon6, mon7/mon8 with the first input always being at a higher voltage than the second. use differential voltage sensing to eliminate voltage offsets or measure supply current. see figure 4. in differential mode, the odd-numbered mon_ input measures the absolute voltage with respect to gnd while the result of the even input is the difference between the odd and even inputs. see figure 4 for the typical differential measurement circuit. internal current-sense amplifier the current-sense inputs, csp/csm, and a current- sense amplifier facilitate power monitoring (see figure 5). the voltage on csp relative to gnd is also monitored by the adc when the current-sense amplifier is enabled with r47h[0]. the conversion results are located in registers r19h and r1ah (see table 10). there are two selectable voltage ranges for csp set by r47h[1], see table 8. although the voltage can be monitored over smbus or jtag, this voltage has no threshold comparators and cannot trigger any faults. regarding the current-sense amplifier, there are four select - able ranges and the adc output for a current-sense conversion is: x adc = (v sense x a v )/1.4v x (2 8 - 1) where x adc is the 8-bit decimal adc result in register r18h, v sense is v csp - v csm, and a v is the current- sense voltage gain set by r47h[3:2]. in addition, there are two programmable current-sense trip thresholds: primary overcurrent and secondary overcurrent. for fast fault detection, the primary overcurrent threshold is implemented with an analog comparator connected to the internal overc signal. the overc signal can be output on one of the gpio_s. see the general-purpose inputs/outputs section for configuring the gpio_ to output the overc signal. the primary threshold is set by: i th = v csth /r sense where i th is the current threshold to be set, v csth is the threshold set by r47h[3:2], and r sense is the value of the sense resistor. see table 8 for a description of r47h. overc depends only on the primary overcurrent threshold. the secondary overcurrent threshold is implemented through adc conversions and digital comparison set by r6ch. the secondary overcurrent threshold includes programmable time delay options located in r73h[6:5]. primary and secondary current- sense faults are enabled/disabled through r47h[0]. general-purpose inputs/outputs gpio1 ? gpio8 are programmable general-purpose inputs/outputs. gpio1?gpio8 are configurable as a manual reset input, a watchdog timer input and output, logic inputs/outputs, fault-dependent outputs. when programmed as outputs, gpio_s are open drain or push- pull. see tables 12 and 13 for more detailed information on configuring gpio1 ? gpio8. figure 4. differential measurement connections figure 5. current-sense amplifier max16065max16066 i load load mon odd mon odd mon even mon even r s power supply power supply + - + + - - *a v csp csm *v csth *adjustable by r47h[3:2] r sense to adc mux v mon load overc max16065 downloaded from: http:///
20 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 8. overcurrent primary threshold and current-sense control table 9 . adc configuration registers register address flash address bit range description 47h 247h [0] 1 = current sense is enabled0 = current sense is disabled [1] 1 = csp full-scale range is 14v0 = csp full-scale range is 7v [3:2] overcurrent primary threshold and current-sense gain setting:00 = 200mv threshold, a v = 6v/v 01 = 100mv threshold, a v = 12v/v 10 = 50mv threshold, a v = 24v/v 11 = 25mv threshold, a v = 48v/v 73h 273h [6:5] overcurrent secondary threshold deglitch:00 = no delay 01 = 4ms 10 = 15ms 11 = 60ms register address flash address bit range description 43h 243h [1:0] adc1 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [3:2] adc2 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [5:4] adc3 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [7:6] adc4 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted downloaded from: http:///
21 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 9. adc configuration registers (continued) register address flash address bit range description 44h 244h [1:0] adc5 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [3:2] adc6 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [5:4] adc7 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [7:6] adc8 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted 45h 245h [1:0] adc9 full-scale range00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [3:2] adc10 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [5:4] adc11 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [7:6] adc12 full-scale range:00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted downloaded from: http:///
22 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 9. adc configuration registers (continued) table 10. adc conversion results (read only) register address flash address bit range description 46h 246h [0] differential conversion adc1?adc2:0 = disabled 1 = enabled [1] differential conversion adc3?adc4:0 = disabled 1 = enabled [2] differential conversion adc5?adc6:0 = disabled 1 = enabled [3] differential conversion adc7?adc8:0 = disabled 1 = enabled register address bit range description 00h [7:0] adc1 result (msb) bits 9?2 01h [7:6] adc1 result (lsb) bits 1?0 02h [7:0] adc2 result (msb) bits 9?2 03h [7:6] adc2 result (lsb) bits 1?0 04h [7:0] adc3 result (msb) bits 9?2 05h [7:6] adc3 result (lsb) bits 1?0 06h [7:0] adc4 result (msb) bits 9?2 07h [7:6] adc4 result (lsb) bits 1?0 08h [7:0] adc5 result (msb) bits 9?2 09h [7:6] adc5 result (lsb) bits 1?0 0ah [7:0] adc6 result (msb) bits 9?2 0bh [7:6] adc6 result (lsb) bits 1?0 0ch [7:0] adc7 result (msb) bits 9?2 0dh [7:6] adc7 result (lsb) bits 1?0 0eh [7:0] adc8 result (msb) bits 9?2 0fh [7:6] adc8 result (lsb) bits 1?0 10h [7:0] adc9 result (msb) bits 9?2 11h [7:6] adc9 result (lsb) bits 1?0 12h [7:0] adc10 result (msb) bits 9?2 13h [7:6] adc10 result (lsb) bits 1?0 14h [7:0] adc11 result (msb) bits 9?2 15h [7:6] adc11 result (lsb) bits 1?0 16h [7:0] adc12 result (msb) bits 9?2 17h [7:6] adc12 result (lsb) bits 1?0 18h [7:0] current-sense adc result 19h [7:0] csp adc output (msb) bits 9?2 1ah [7:6] csp adc output (lsb) bits 1?0 downloaded from: http:///
23 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 when gpio1 ? gpio8 are configured as general- purpose inputs/outputs, read values from the gpio_ ports through r1eh and write values to gpio_s through r3eh. note that r3eh has a corresponding flash register, which programs the default state of a general-purpose output. see table 11 for more information on reading and writing to the gpio_. fault1 and fault2 gpio1 ? gpio8 are configurable as dedicated fault outputs, fault1 or fault2. fault outputs can assert on one or more overvoltage, undervoltage, or early warning conditions for selected inputs, as well as the secondary overcurrent comparator. fault1 and fault2 dependencies are set using registers r36h to r3ah. see table 14. when a fault output depends on more than one mon_, the fault output asserts when one or more mon_ exceeds a programmed threshold voltage. these fault outputs act independently of the critical fault system, described in the critical faults section. table 11. gpio_ state registers table 12. gpio_ configuration registers register address flash address bit range description 1eh ? [0] gpio1 input state [1] gpio2 input state [2] gpio3 input state [3] gpio4 input state [4] gpio5 input state [5] gpio6 input state [6] gpio7 input state [7] gpio8 input state 3eh 23eh [0] gpio1 output state [1] gpio2 output state [2] gpio3 output state [3] gpio4 output state [4] gpio5 output state [5] gpio6 output state [6] gpio7 output state [7] gpio8 output state register address flash address bit range description 3fh 23fh [2:0] gpio1 configuration [5:3] gpio2 configuration [7:6] gpio3 configuration (lsb) 40h 240h [0] gpio3 configuration (msb) [3:1] gpio4 configuration [6:4] gpio5 configuration [7] gpio6 configuration (lsb) 41h 241h [1:0] gpio6 configuration (msb) [4:2] gpio7 configuration [7:5] gpio8 configuration downloaded from: http:///
24 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 12. gpio_ configuration registers (continued) table 13. gpio_ function configuration bits register address flash address bit range description 42h 242h [0] output configuration for gpio1:0 = push-pull 1 = open drain [1] output configuration for gpio2:0 = push-pull 1 = open drain [2] output configuration for gpio3:0 = push-pull 1 = open drain [3] output configuration for gpio4:0 = push-pull 1 = open drain [4] output configuration for gpio5:0 = push-pull 1 = open drain [5] output configuration for gpio6:0 = push-pull 1 = open drain [6] output configuration for gpio7:0 = push-pull 1 = open drain [7] output configuration for gpio8:0 = push-pull 1 = open drain gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpio8 000 logic input logic input logic input logic input logic input logic input logic input logic input 001 logic output logic output logic output logic output logic output logic output logic output logic output 010 fault2 output fault2 output fault2 output fault2 output fault2 output fault2 output fault2 output fault2 output 011 fault1 output fault1 output faultpu output fault1 output fault1 output fault1 output fault1 output faultpu output 100 any_fault output reset2 output any_fault output any_fault output any_fault output reset2 output any_fault output reset2 output 101 overc output overc output overc output overc output overc output overc output overc output overc output 110 mr input wdo output mr input wdo output mr input wdo output mr input wdo output 111 wdi input ? ? extfault input/output en2 input margin input en2 input extfault input/output downloaded from: http:///
25 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 any_fault gpio1, gpio3, gpio4, gpio5, and gpio7 are configurable to assert low during any fault condition. this includes power-up, power-down fault conditions as well as conditions where fault1 or fault2 assert. second enable (en2) gpio5 and gpio7 are configurable as the enable input for the secondary sequence. see the multiple sequencing groups section for more details. table 14. fault1 and fault2 dependencies register address flash address bit range description 36h 236h 0 1 = fault1 depends on mon1 1 1 = fault1 depends on mon2 2 1 = fault1 depends on mon3 3 1 = fault1 depends on mon4 4 1 = fault1 depends on mon5 5 1 = fault1 depends on mon6 6 1 = fault1 depends on mon7 7 1 = fault1 depends on mon8 37h 237h 0 1 = fault1 depends on mon9 1 1 = fault1 depends on mon10 2 1 = fault1 depends on mon11 3 1 = fault1 depends on mon12 4 1 = fault1 depends on the overvoltage thresholds of the inputs selected by r36h and r37h[3:0] 5 1 = fault1 depends on the undervoltage thresholds of the inputs selected by r36h and r37h[3:0] 6 1 = fault1 depends on the early warning thresholds of the inputs selected by r36h and r37h[3:0] 7 0 = fault1 is an active-low digital output1 = fault1 is an active-high digital output 38h 238h [0] 1 = fault2 depends on mon1 [1] 1 = fault2 depends on mon2 [2] 1 = fault2 depends on mon3 [3] 1 = fault2 depends on mon4 [4] 1 = fault2 depends on mon5 [5] 1 = fault2 depends on mon6 [6] 1 = fault2 depends on mon7 [7] 1 = fault2 depends on mon8 downloaded from: http:///
26 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 overcurrent comparator ( overc ) gpio1 to gpio8 are configurable to assert low when the voltage across csp and csm exceed the primary overcurrent threshold. see the internal current-sense amplifier section for more details. fault-on power-up ( faultpu ) gpio3 and gpio8 are configurable to indicate a fault during power-up or power-down on the secondary sequence. this output asserts low when a mon_ input exceeds the overvoltage or undervoltage threshold. the sequencer will still enter the fault state and turn off all the en_out_ outputs assigned to the secondary sequence. manual reset ( mr) gpio1, gpio3, gpio5, and gpio7 are configurable to act as an active-low manual reset input, mr . drive mr low to assert reset. reset remains asserted for the selected reset timeout period after mr transitions from low to high. see the reset2 output section for more information on selecting a reset timeout period. reset2 output gpio2, gpio6, and gpio8 are configurable to act as a reset indicator related to the secondary sequence. reset2 asserts during power-up/power-down and deasserts following the reset timeout period once the power-up of the secondary sequence is complete. the secondary power-up sequence is completed when any mon_ inputs assigned to slot 12 exceed the undervolt - age thresholds and slot 12 sequence delay expires. when no mon_ inputs are assigned to slot 12, the power-up sequence is complete after the slot sequence delay expires. reset2 shares configuration bits with reset with the exception of polarity (active-high or active-low) and output type (push-pull or open drain), see table 23. during normal monitoring, reset2 can be configured to assert when any combination of mon_ inputs violates configurable combinations of thresholds: undervoltage, overvoltage, or early warning. select the combination of thresholds using r3bh[1:0], and select the combination of mon_ inputs using r3ch[7:1] and r3dh[4:0]. note that mon_ inputs in the secondary sequence configured as critical faults will always cause reset2 to assert regardless of these configuration bits.reset2 can be configured as push-pull or open drain using the appropriate gpio_ configuration bit in r42h (see table 12), and is always active-low. select the reset timeout for reset and reset2 by loading a value from table 5 into r3bh[7:4]. reset and reset2 can be forced to assert by writing a ?1? into r3ch[0]. reset2 remains asserted for the reset timeout period after a ?0? is written into r3ch[0]. watchdog input (wdi) and output ( wdo ) gpio2, gpio4, gpio6, and gpio8 are configurable as the watchdog timer output, wdo . gpio1 is configurable as wdi. see table 24 for configuration details. wdo is an active-low output. see the watchdog timer section for more information about the operation of the watchdog timer. table 14. fault1 and fault2 dependencies (continued) register address flash address bit range description 39h 239h [0] 1 = fault2 depends on mon9 [1] 1 = fault2 depends on mon10 [2] 1 = fault2 depends on mon11 [3] 1 = fault2 depends on mon12 [4] 1 = fault2 depends on the overvoltage thresholds of the inputs selected by r38h and r39h[3:0] [5] 1 = fault2 depends on the undervoltage thresholds of the inputs selected by r38h and r39h[3:0] [6] 1 = fault2 depends on the early warning thresholds of the inputs selected by r38h and r39h[3:0] [7] 0 = fault2 is an active-low digital output1 = fault2 is an active-high digital output 3ah 23ah [0] 1 = fault1 depends on secondary overcurrent comparator [1] 1 = fault2 depends on secondary overcurrent comparator [7:2] reserved downloaded from: http:///
27 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 external fault ( extfault) gpio4 and gpio8 are configurable as the external fault input/output. when configured as push-pull, extfault signals that a critical fault has occurred on one or more monitored voltages or current. when configured as open-drain, extfault can be asserted low by an external circuit to trigger a critical fault. this signal can be used to cascade multiple max16065/max16066s. two configuration bits determine the behavior of the max16065/max16066 when extfault is pulled low by some other device. register bit r72h[5], if set to a ?1?, causes the sequencer state machine to enter the fault state, deasserting all the outputs, when extfault is pulled low. when this happens, the flag bit r1ch[5] gets set to indicate the cause of the fault. if register bit r6dh[2] is set in addition to r72h[5], extfault going low triggers a nonvolatile fault log operation. faults the max16065/max16066 monitor the input (mon_) channels and compare the results with an overvolt - age threshold, an undervoltage threshold, and a selectable overvoltage or undervoltage early warning threshold. based on these conditions, the max16065/ max16066 assert various fault outputs and save specific information about the channel conditions and voltages into the nonvolatile flash. once a critical fault event occurs, the failing channel condition, adc conversions at the time of the fault, or both can be saved by configuring the event logger. the event logger records a single failure in the internal flash and sets a lock bit that protects the stored fault data from accidental erasure on a subsequent power-up. an overvoltage event occurs when the voltage at a monitored input exceeds the overvoltage threshold for that input. an undervoltage event occurs when the voltage at a monitored input falls below the undervolt - age threshold. fault thresholds are set in registers r48h to r6ch as shown in table 15. disabled inputs are not monitored for fault conditions and are skipped over by the input multiplexer. only the upper 8 bits of a conversion result are compared with the programmed fault thresholds. the general-purpose inputs/outputs (gpio1 to gpio8) can be configured as any_fault outputs or dedicated fault1 and fault2 outputs to indicate fault conditions. these fault outputs are not masked by the critical fault enable bits shown in table 18. see the general- purpose inputs/outputs section for more information on configuring gpio_s as fault outputs. deglitch fault conditions are detected at the end of each conversion. when the voltage on an input falls outside a monitored threshold for one acquisition, the input multiplexer remains on that channel and performs several successive conversions. to trigger a fault, the input must stay outside the threshold for a certain number of acquisitions as determined by the deglitch setting in r73h[6:5] and r74h[6:5] (see table 16). fault flags fault flags indicate the fault status of a particular input. the fault flag of any monitored input in the device can be read at any time from registers r1bh and r1ch, as shown in table 17. clear a fault flag by writing a ?1? to the appropriate bit in the flag register. unlike the fault signals sent to the fault outputs, these bits are masked by the critical fault enable bits (see table 18). the fault flag is only set when the matching enable bit in the critical fault enable register is also set. if a gpio_ is configured as an open-drain extfault input/output, and extfault is pulled low by an external circuit, bit r1ch[5] is set.if a fault occurs during the secondary sequence group, the slot number where the failure occurred is stored in r1dh.the smbus alert bit is set if the max16065/max16066 have asserted the smbus alert output. clear by writing a ?1?. see the smbalert section for more details. downloaded from: http:///
28 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 15. fault threshold registers register address flash address bit range description 48h 248h [7:0] mon1 secondary threshold 49h 249h [7:0] mon1 overvoltage threshold 4ah 24ah [7:0] mon1 undervoltage threshold 4bh 24bh [7:0] mon2 secondary threshold 4ch 24ch [7:0] mon2 overvoltage threshold 4dh 24dh [7:0] mon2 undervoltage threshold 4eh 24eh [7:0] mon3 secondary threshold 4fh 24fh [7:0] mon3 overvoltage threshold 50h 250h [7:0] mon3 undervoltage threshold 51h 251h [7:0] mon4 secondary threshold 52h 252h [7:0] mon4 overvoltage threshold 53h 253h [7:0] mon4 undervoltage threshold 54h 254h [7:0] mon5 secondary threshold 55h 255h [7:0] mon5 overvoltage threshold 56h 256h [7:0] mon5 undervoltage threshold 57h 257h [7:0] mon6 secondary threshold 58h 258h [7:0] mon6 overvoltage threshold 59h 259h [7:0] mon6 undervoltage threshold 5ah 25ah [7:0] mon7 secondary threshold 5bh 25bh [7:0] mon7 overvoltage threshold 5ch 25ch [7:0] mon7 undervoltage threshold 5dh 25dh [7:0] mon8 secondary threshold 5eh 25eh [7:0] mon8 overvoltage threshold 5fh 25fh [7:0] mon8 undervoltage threshold 60h 260h [7:0] mon9 secondary threshold 61h 261h [7:0] mon9 overvoltage threshold 62h 262h [7:0] mon9 undervoltage threshold 63h 263h [7:0] mon10 secondary threshold 64h 264h [7:0] mon10 overvoltage threshold 65h 265h [7:0] mon10 undervoltage threshold 66h 266h [7:0] mon11 secondary threshold 67h 267h [7:0] mon11 overvoltage threshold 68h 268h [7:0] mon11 undervoltage threshold 69h 269h [7:0] mon12 secondary threshold 6ah 26ah [7:0] mon12 overvoltage threshold 6bh 26bh [7:0] mon12 undervoltage threshold 6ch 26ch [7:0] secondary overcurrent threshold downloaded from: http:///
29 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 critical faults during normal operation, a fault condition can be configured to shut down all the en_out_s and store fault information in the flash memory by setting the appropriate critical fault enable bits. during power- up and power-down, all sequenced mon_ inputs are considered critical. faults during power-up and power- down always cause the en_out_s to turn off and can store fault information in the flash memory, depending on the contents of r6dh[1:0]. set the appropriate critical fault enable bits in registers r6eh to r72h (see table 18) for a fault condition to trigger a critical fault. logged fault information is stored in flash registers r200h to r20fh (see table 19). after fault information is logged, the flash is locked and must be unlocked to enable a new fault log to be stored. write a ?0? to r8ch[1] to unlock the fault flash. fault information can be configured to store adc conversion results and/or fault flags in registers. select the critical fault configuration in r6dh[1:0]. set r6dh[1:0] to ?11? to turn off the fault logger. all stored adc results are 8 bits wide. power-up/power-down faults all en_out_s deassert when an overvoltage or undervolt - age fault is detected during power-up/power-down and the max16065/max16066 return to the power-off condi - tion. fault information can be stored to flash depending on r6dh[1:0], see table 18. gpio3 and gpio8 can be configured as power-up fault outputs ( faultpu ). autoretry/latch mode the max16065/max16066 can be configured for one of two fault management methods: autoretry or latch-on fault. set r74h[4:3] to ?00? to select the latch-on- fault mode. in this configuration, en_out_s deassert after a critical fault event. the device does not reinitiate the power-up sequence until en is toggled or the software enable bit is toggled. see the enable and enable2 section for more information on setting the software enable bit. set r74h[4:3] to a value other than ?00? to select autoretry mode (see table 20). in this configuration, the device shuts down after a critical fault event then restarts following a configurable delay. use r74h[2:0] to select an table 16. deglitch configuration table 17. fault flags register address flash address bit range description 73h 273h [6:5] overcurrent comparator deglitch time:00 = no deglitch 01 = 4ms 10 = 15ms 11 = 60ms 74h 274h [6:5] voltage comparator deglitch configuration:00 = 2 cycles 01 = 4 cycles 10 = 8 cycles 11 = 16 cycles register address bit range description 1bh [0] mon1 [1] mon2 [2] mon3 [3] mon4 [4] mon5 [5] mon6 [6] mon7 [7] mon8 downloaded from: http:///
30 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 17. fault flags (continued) table 18. critical fault configuration register address bit range description 1ch [0] mon9 [1] mon10 [2] mon11 [3] mon12 [4] overcurrent [5] external fault ( extfault ) [6] smb alert 1dh [4:0] slot where failure occurred during secondary sequence [7:5] reserved register address flash address bit range description 6dh 26dh [1:0] fault information to log:00 = save failed line flags and adc values in flash 01 = save only failed line flags in flash 10 = save only adc values in flash 11 = do not save anything [2] 1 = fault log triggered when extfault is pulled low externally [7:3] not used 6eh 26eh [0] 1 = fault log triggered when mon1 is below its undervoltage threshold [1] 1 = fault log triggered when mon2 is below its undervoltage threshold [2] 1 = fault log triggered when mon3 is below its undervoltage threshold [3] 1 = fault log triggered when mon4 is below its undervoltage threshold [4] 1 = fault log triggered when mon5 is below its undervoltage threshold [5] 1 = fault log triggered when mon6 is below its undervoltage threshold [6] 1 = fault log triggered when mon7 is below its undervoltage threshold [7] 1 = fault log triggered when mon8 is below its undervoltage threshold 6fh 26fh [0] 1 = fault log triggered when mon9 is below its undervoltage threshold [1] 1 = fault log triggered when mon10 is below its undervoltage threshold [2] 1 = fault log triggered when mon11 is below its undervoltage threshold [3] 1 = fault log triggered when mon12 is below its undervoltage threshold [4] 1 = fault log triggered when mon1 is above its overvoltage threshold [5] 1 = fault log triggered when mon2 is above its overvoltage threshold [6] 1 = fault log triggered when mon3 is above its overvoltage threshold [7] 1 = fault log triggered when mon4 is above its overvoltage threshold downloaded from: http:///
31 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 18. critical fault configuration (continued) table 19. nonvolatile fault log registers register address flash address bit range description 70h 270h [0] 1 = fault log triggered when mon5 is above its overvoltage threshold [1] 1 = fault log triggered when mon6 is above its overvoltage threshold [2] 1 = fault log triggered when mon7 is above its overvoltage threshold [3] 1 = fault log triggered when mon8 is above its overvoltage threshold [4] 1 = fault log triggered when mon9 is above its overvoltage threshold [5] 1 = fault log triggered when mon10 is above its overvoltage threshold [6] 1 = fault log triggered when mon11 is above its overvoltage threshold [7] 1 = fault log triggered when mon12 is above its overvoltage threshold 71h 271h [0] 1 = fault log triggered when mon1 is above/below the early threshold warning [1] 1 = fault log triggered when mon2 is above/below the early threshold warning [2] 1 = fault log triggered when mon3 is above/below the early threshold warning [3] 1 = fault log triggered when mon4 is above/below the early threshold warning [4] 1 = fault log triggered when mon5 is above/below the early threshold warning [5] 1 = fault log triggered when mon6 is above/below the early threshold warning [6] 1 = fault log triggered when mon7 is above/below the early threshold warning [7] 1 = fault log triggered when mon8 is above/below the early threshold warning 72h 272h [0] 1 = fault log triggered when mon9 is above/below the early threshold warning [1] 1 = fault log triggered when mon10 is above/below the early threshold warning [2] 1 = fault log triggered when mon11 is above/below the early threshold warning [3] 1 = fault log triggered when mon12 is above/below the early threshold warning [4] 1 = fault log triggered when overcurrent early threshold is exceeded [5] 1 = extfault pulled low externally causes sequencer to enter fault state, turning off all en_out_s0 = extfault pulled low externally does not cause sequencer to enter fault state [7:6] reserved flash address bit range description 200h [4:0] sequencer state where the fault has happened (see table 1 for state codes) [7:5] not used 201h [0] fault log triggered on mon1 [1] fault log triggered on mon2 [2] fault log triggered on mon3 [3] fault log triggered on mon4 [4] fault log triggered on mon5 [5] fault log triggered on mon6 [6] fault log triggered on mon7 [7] fault log triggered on mon8 downloaded from: http:///
32 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 19. nonvolatile fault log registers (continued) table 20. autoretry configuration flash address bit range description 202h [0] fault log triggered on mon9 [1] fault log triggered on mon10 [2] fault log triggered on mon11 [3] fault log triggered on mon12 [4] fault log triggered on overcurrent [5] fault log triggered on extfault [7:6] not used 203h [7:0] mon1 adc output bits 9?2 204h [7:0] mon2 adc output bits 9?2 205h [7:0] mon3 adc output bits 9?2 206h [7:0] mon4 adc output bits 9?2 207h [7:0] mon5 adc output bits 9?2 208h [7:0] mon6 adc output bits 9?2 209h [7:0] mon7 adc output bits 9?2 20ah [7:0] mon8 adc output bits 9?2 20bh [7:0] mon9 adc output bits 9?2 20ch [7:0] mon10 adc output bits 9?2 20dh [7:0] mon11 adc output bits 9?2 20eh [7:0] mon12 adc output bits 9?2 20fh [7:0] current-sense adc output bits 9?2 register address flash address bit range description 74h 274h [2:0] retry delay:000 = 20ms 001 = 40ms 010 = 80ms 011 = 150ms 100 = 280ms 101 = 540ms 110 = 1s 111 = 2s [4:3] autoretry/latch mode:00 = latch 01 = retry 1 time 10 = retry 3 times 11 = always retry downloaded from: http:///
33 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 autoretry delay from 20ms to 2s. see table 20 for more information on setting the autoretry delay. when fault information is stored in flash (see the critical faults section) and autoretry mode is selected, set an autoretry delay greater than the time required for the storing operation. when fault information is stored in flash and latch-on-fault mode is chosen, toggle en or reset the software enable bit only after the comple - tion of the storing operation. when saving information about the failed lines only, ensure a delay of at least 150ms before the restart procedure. otherwise, ensure a minimum 280ms timeout, to ensure that adc conversions are completed and values are stored correctly in flash. programmable ouputs (en_out1?en_out12) the max16065 includes twelve programmable out - puts, and the max16066 includes eight programmable outputs. these outputs are capable of connecting to either the enable (en) inputs of a dc-dc or ldo power supply, or to drive the gate of an n-channel mosfet in charge-pump mode. selectable output configurations include: active-low or active-high, open drain or push- pull. en_out1?en_out8 can act as charge-pump outputs, en_out9?en_out12 can be configured as general-purpose inputs or general-purpose outputs. use registers r30h to r33h to configure outputs. see table 21 for detailed information on configuring en_out1?en_out12. in charge-pump configuration, en_out1?en_out8 act as high-voltage charge-pump outputs to drive up to eight external n-channel mosfets. during sequencing, an en_ out_ output set to the charge-pump configuration outputs 11v relative to gnd. see the sequencing section for more detailed information on power-supply sequencing.in open-drain output configuration, connect an exter - nal pullup resistor from the output to an external voltage up to 5.5v (en_out9?en_out12) or 14v (en_out1? en_out8). choose the pullup resistor depending on the number of devices connected to the open-drain output and the allowable current consumption. the open-drain output configuration allows wire-ored connection. in push-pull configuration, the max16065/max16066?s programmable outputs are referenced to v dbp . en_out_s as gpio_ (max16065 only) en_out9 to en_out12 can be configured as gpio_ by setting the sequencing slot assignments in r88h and r89h to ?1101? and ?1110?, see tables 5 and 6. if an en_out_ is configured as a general-purpose input, the state of the pin can be read from r1fh (see table 22). if an en_out_ is configured as a general-purpose output, it is controlled by r34h. table 21. en_out1?en_out12 configuration register address flash address bit range description 30h 230h [1:0] en_out1 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull [3:2] en_out2 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull [5:4] en_out3 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull [7:6] en_out4 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull downloaded from: http:///
34 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 21. en_out1?en_out12 configuration (continued) register address flash address bit range description 31h 231h [1:0] en_out5 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull [3:2] en_out6 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull [5:4] en_out7 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull [7:6] en_out8 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull 32h (max16065 only) 232h [1:0] en_out9 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull [3:2] en_out10 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull [5:4] en_out11 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull [7:6] en_out12 configuration:00 = active-low, open drain 01 = active-high, open drain 10 = active-low, push-pull 11 = active-high, push-pull downloaded from: http:///
35 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 21. en_out1?en_out12 configuration (continued) en_out_ state during power-up when v cc is ramped from 0 to the operating supply voltage, the en_out_ output is high impedance until v cc reaches uvlo and then en_out_ goes into the configured deasserted state after the boot-up relay. see figures 6 and 7. configure reset as an active-low push-pull or open- drain output pulled up to v cc through a 10k i resistor for figures 6 and 7. reset output the reset output, reset, indicates the status of the pri - mary sequence. it asserts during power-up/power-down and deasserts following the reset timeout period once the power-up sequence is complete. the power-up sequence is complete when any mon_ inputs assigned to the final slot exceed the undervoltage thresholds and final sequence delay expires. when no mon_ inputs are assigned to the final slot, the power-up sequence is complete after the slot sequence delay expires. during normal monitoring, reset can be configured to assert when any combination of mon_ inputs violates configurable combinations of thresholds: undervoltage, overvoltage, or early warning. select the combination of thresholds using r3bh[1:0], and select the combination of mon_ inputs using r3ch[7:1] and r3dh[4:0]. note that mon_ inputs configured as critical faults will always cause reset to assert regardless of these configuration bits. reset can be configured as push-pull or open drain using r3bh[3], and active-high or active-low using r3bh[2]. select the reset timeout by loading a value from table 23 into r3bh[7:4]. reset can be forced to assert by writing a ?1? into r3ch[0]. reset remains asserted for the reset timeout period after a ?0? is written into r3ch[0]. see table 23. the current state of reset can be checked by reading r20h[0]. register address flash address bit range description 33h 233h [0] en_out1 charge-pump output configuration:0 = charge-pump output disabled 1 = charge-pump output enabled (active-high) [1] en_out2 charge-pump output configuration:0 = charge-pump output disabled 1 = charge-pump output enabled (active-high) [2] en_out3 charge-pump output configuration:0 = charge-pump output disabled 1 = charge-pump output enabled (active-high) [3] en_out4 charge-pump output configuration:0 = charge-pump output disabled 1 = charge-pump output enabled (active-high) [4] en_out5 charge-pump output configuration:0 = charge-pump output disabled 1 = charge-pump output enabled (active-high) [5] en_out6 charge-pump output configuration:0 = charge-pump output disabled 1 = charge-pump output enabled (active-high) [6] en_out7 charge-pump output configuration:0 = charge-pump output disabled 1 = charge-pump output enabled (active-high) [7] en_out8 charge-pump output configuration:0 = charge-pump output disabled 1 = charge-pump output enabled (active-high) downloaded from: http:///
36 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 watchdog timer the watchdog timer operates together with or indepen - dently of the max16065/max16066. when operating in dependent mode, the watchdog is not activated until the sequencing is complete and reset is deasserted. when operating in independent mode, the watchdog timer is independent of the sequencing operation and activates immediately after v cc exceeds the uvlo threshold and the boot phase is complete. set r73h[4] to ?0? to configure the watchdog in dependent mode. set r73h[4] to ?1? to configure the watchdog in independent mode. see table 24 for more information on configuring the watchdog timer in dependent or independent mode. dependent watchdog timer operation use the watchdog timer to monitor f p activity in two modes. flexible timeout architecture provides an adjust - able watchdog startup delay of up to 300s, allowing complicated systems to complete lengthy boot-up rou - tines. an adjustable watchdog timeout allows the super - visor to provide quick alerts when processor activity fails. after each reset event (v cc drops below uvlo then returns above uvlo, software reboot, manual reset ( mr ), en input going low then high, or watchdog reset) and once sequencing is complete, the watchdog startup delay provides an extended time for the system to power up and fully initialize all f p and system components before assuming responsibility for routine watchdog updates. set r76h[6:4] to a value other than ?000? to enable the watchdog startup delay. set r76h[6:4] to ?000? to disable the watchdog startup delay. table 22. en_out_ gpio_ state registers register address flash address bit range description 1fh ? [0] en_out9 input state [1] en_out10 input state [2] en_out11 input state [3] en_out12 input state 34h 234h [0] 1 = assert en_out9 [1] 1 = assert en_out10 [2] 1 = assert en_out11 [3] 1 = assert en_out12 figure 6. reset and en_out_ during power-up, en_out_ in open-drain active-low configuration max16065 fig06 20ms/div v cc 2v/diven_out _ 2v/div 0vreset 2v/div 0v 0v max16065 fig07 10ms/div v cc 2v/diven_out _ 2v/div 0vreset 2v/div 0v 0v high-z asserted low uvlo figure 7. reset and en_out_ during power-up, en_out_ in push-pull active-high configuration downloaded from: http:///
37 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 table 23. reset output configuration register address flash address bit range description 3bh 23bh [1:0] reset output depends on:00 = undervoltage threshold violations 01 = early warning threshold violations 10 = overvoltage threshold violations 11 = undervoltage or overvoltage threshold violations [2] 0 = active-low1 = active-high [3] 1 = push-pull0 = open drain [7:4] reset timeout period:0000 = 25 f s 0001 = 1.5ms0010 = 2.5ms 0011 = 4ms 0100 = 6ms 0101 = 10ms 0110 = 15ms 0111 = 25ms 1000 = 40ms 1001 = 60ms 1010 = 100ms 1011 = 150ms 1100 = 250ms 1101 = 400ms 1110 = 600ms 1111 = 1s 3ch 23ch [0] reset soft trigger:0 = normal reset behavior 1 = force reset to assert [1] 1 = reset depends on mon1 [2] 1 = reset depends on mon2 [3] 1 = reset depends on mon3 [4] 1 = reset depends on mon4 [5] 1 = reset depends on mon5 [6] 1 = reset depends on mon6 [7] 1 = reset depends on mon7 3dh 23dh [0] 1 = reset depends on mon8 [1] 1 = reset depends on mon9 [2] 1 = reset depends on mon10 [3] 1 = reset depends on mon11 [4] 1 = reset depends on mon12 [7:5] reserved downloaded from: http:///
38 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 the normal watchdog timeout period, t wdi , begins after the first transition on wdi before the conclusion of the long startup watchdog period, t wdi_startup (figure 8). during the normal operating mode, wdo asserts if the f p does not toggle wdi with a valid transition (high-to- low or low-to-high) within the standard timeout period, t wdi . wdo remains asserted until wdi is toggled or reset is asserted (figure 9). while en is low, the watchdog timer is in reset. the watchdog timer does not begin counting until the power- on mode is reached and reset is deasserted. the watchdog timer is reset and wdo deasserts any time reset is asserted (figure 10). the watchdog timer will be held in reset while reset is asserted. the watchdog can be configured to control the reset output as well as the wdo output. reset asserts for the reset timeout, t rp , when the watchdog timer expires and the watchdog reset output enable bit (r76h[7]) is set to ?1.? when reset is asserted, the watchdog timer is cleared and wdo is deasserted, therefore, wdo pulses low for a short time (approximately 1 f s) when the watchdog timer expires. reset is not affected by the watchdog timer when the watchdog reset output enable bit (r76h[7]) is set to ?0.? if a reset is asserted by the watchdog timeout, the wdreset bit is set to ?1.? a connected processor can check this bit to see the reset was due to a watchdog timeout. see table 24 for more information on configuring watchdog functionality. figure 8. normal watchdog startup sequence figure 9. watchdog timer operation last mon_wdi v th t wdi_startup < t wdi t rp reset < t wdi wdiwdo 0v v cc 0v v cc < t wdi < t wdi < t wdi < t wdi > t wdi < t wdi < t wdi t wdi downloaded from: http:///
39 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 figure 10. watchdog startup sequence with watchdog reset output enable bit set to ?1? table 24. watchdog configuration wdiwdo 0v0v v cc v cc 0v v cc < t wdi 1s reset < t wdi t wdi t rp < t wdi_startup register address flash address bit range description 73h 273h [4] 1 = independent mode0 = dependent mode 76h 276h [7] 1 = watchdog affects reset output0 = watchdog does not affect reset output [6:4] watchdog startup delay:000 = no initial timeout 001 = 30s 010 = 40s 011 = 80s 100 = 120s 101 = 160s 110 = 220s 111 = 300s [3:0] watchdog timeout:0000 = watchdog disabled 0001 = 1ms 0010 = 2ms 0011 = 4ms 0100 = 8ms 0101 = 14ms 0110 = 27ms 0111 = 50ms 1000 = 100ms 1001 = 200ms 1010 = 400ms 1011 = 750ms 1100 = 1.4s 1101 = 2.7s 1110 = 5s 1111 = 10s downloaded from: http:///
40 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 independent watchdog timer operation when r73h[4] is ?1? the watchdog timer operates in independent mode. in independent mode, the watchdog timer operates as if it were a separate device. the watch - dog timer is activated immediately upon v cc exceeding uvlo and once the boot-up sequence is finished. when reset is asserted by the sequencer state machine, the watchdog timer and wdo are not affected. there will be a startup delay if r76h[6:4] is set to a value different than ?000.? if r76h[6:4] is set to ?000,? there will not be a startup delay. see table 24 for delay times. in independent mode, if the watchdog reset output enable bit r76h[7] is set to ?1,? when the watchdog timer expires, wdo asserts then reset asserts. wdo will then deassert. wdo will be low for approximately 1 f s. if the watchdog reset output enable bit (r76h[7]) is set to ?0,? when the wdt expires, wdo asserts but reset is not affected. user-defined register register r8ah provides storage space for a user-defined configuration or firmware version number. note that this register controls the contents of the jtag usercode register bits 7:0. the user-defined register is stored at r28ah in the flash memory. memory lock bits register r8ch contains the lock bits for the configuration registers, configuration flash, user flash and fault register lock. see table 25 for details. smbus-compatible interface the max16065/max16066 feature an smbus- compatible, 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate bidirectional communication between the max16065/max16066 and the master device at clock rates up to 400khz. figure 1 shows the 2-wire interface timing diagram. the max16065/max16066 are transmit/ receive slave-only devices, relying upon a master device to generate a clock signal. the master device (typically a microcontroller) initiates a data transfer on the bus and generates scl to permit that transfer. a master device communicates to the max16065/ max16066 by transmitting the proper address followed by a command and/or data words. the slave address input, a0, is capable of detecting four different states, allowing multiple identical devices to share the same serial bus. the slave address is described further in the slave address section. each transmit sequence is framed by a start (s) or repeated start (sr) con - dition and a stop (p) condition. each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. scl is a logic input, while sda is an open-drain input/output. scl and sda both require external pullup resistors to generate the logic-high voltage. use 4.7k i for most applications. table 25. memory lock bits register address flash address bit range description 8ch 28ch 0 configuration register lock:1 = locked 0 = unlocked 1 flash fault register lock:1 = locked 0 = unlocked 2 flash configuration lock:1 = locked 0 = unlocked 3 user flash lock:1 = locked 0 = unlocked downloaded from: http:///
41 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 bit transfer each clock pulse transfers one data bit. the data on sda must remain stable while scl is high (figure 11); other - wise the max16065/max16066 detect a start or stop condition (figure 12) from the master. sda and scl idle high when the bus is not busy. start and stop conditions both scl and sda idle high when the bus is not busy. a master device signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high. the master device issues a stop condition by transitioning sda from low to high while scl is high. a stop condition frees the bus for another transmission. the bus remains active if a repeated start condition is generated, such as in the block read protocol (see figure 1). early stop conditions the max16065/max16066 recognize a stop condition at any point during transmission except if a stop condition occurs in the same high pulse as a start condition. this condition is not a legal smbus format; at least one clock pulse must separate any start and stop condition. repeated start conditions a repeated start can be sent instead of a stop condition to maintain control of the bus during a read operation. the start and repeated start conditions are functionally identical. acknowledge the acknowledge bit (ack) is the 9th bit attached to any 8-bit data word. the receiving device always generates an ack. the max16065/max16066 generate an ack when receiving an address or data by pulling sda low during the 9th clock period (figure 13). when transmit - ting data, such as when the master device reads data back from the max16065/max16066, the device waits for the master device to generate an ack. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master can reattempt communication at a later time. the max16065/max16066 generate a nack after the command byte received dur - ing a software reboot, while writing to the flash, or when receiving an illegal memory address. slave address use the slave address input, a0, to allow multiple identi - cal devices to share the same serial bus. connect a0 to gnd, dbp (or an external supply voltage greater than 2v), scl, or sda to set the device address on the bus. see table 27 for a listing of all possible 7-bit addresses. the slave address can also be set to a custom value by loading the address into register r8bh[6:0]. see table 26. if r8bh[6:0] is loaded with 00h, the address is set by input a0. do not set the address to 09h or 7fh to avoid address conflicts. the slave address setting takes effect immediately after writing to the register. packet error checking (pec) the max16065/max16066 feature a pec mode that is useful for improving the reliability of the communication bus by detecting bit errors. by enabling pec, an extra crc-8 error check byte is added in the data string during each read and/or write sequence. enable pec by writing a ?1? to r8bh[7]. the crc-8 byte is calculated using the polynomial c = x 8 + x 2 + x + 1 figure 11. bit transfer data line stable, data valid sda scl change of data allowed figure 12. start and stop conditions p s start condition sda scl stop condition downloaded from: http:///
42 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 the pec calculation includes all bytes in the transmis - sion, including address, command, and data. the pec calculation does not include ack, nack, start, stop, or repeated start. command codes the max16065/max16066 use eight command codes for block read, block write, and other commands. see table 28 for a list of command codes. to initiate a software reboot, send a7h using the send byte format. a software-initiated reboot is functionally the same as a hardware-initiated power-on reset. during boot-up, flash configuration data in the range of 230h to 28ch is copied to r30h to r8ch registers in the default page. send command code a8h to trigger a fault store to flash. configure the critical fault log control register (r6dh) to store adc conversion results and/or fault flags. while in the flash page, send command code a9h to access the flash page (addresses from 200h to 28dh). once command code a9h has been sent, all addresses are recognized as flash addresses only. send command code aah to return to the default page (addresses from 000h to 08dh). send command code abh to access the user flash-page (addresses from 300h to 39fh and 3b0h to 3ffh), and send command code ach to return to the flash page. restrictions when writing to flash flash must be written to 8 bytes at a time. the initial address must be aligned to 8-byte boundaries?the 3 lsbs of the initial address must be ?000?. write the 8 bytes using a single block-write command or using 8 successive write byte commands. table 26. smbus settings register table 27. setting the smbus slave address r = read/write select bit. table 28. command codes register address flash address bit range description 8bh 28bh [6:0] smbus slave address register. set to 00h to use a0 pin address setting. [7] 1 = enable pec (packet error check). slave addresses a0 slave address 0 1010 000r 1 1010 001r scl 1010 010r sda 1010 011r command code action a5h block write a6h block read a7h reboot flash in register file a8h trigger emergency save to flash a9h flash page access on aah flash page access off abh user flash access on (must be in flash page already) ach user flash access off (return to flash page) downloaded from: http:///
43 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 send byte the send byte protocol allows the master device to send one byte of data to the slave device (see figure 14). the send byte presets a register pointer address for a subsequent read or write. the slave sends a nack instead of an ack if the master tries to send a memory address or command code that is not allowed. if the master sends a5h or a6h, the data is ack, because this could be the start of the write block or read block. if the master sends a stop condition before the slave asserts an ack, the internal address pointer does not change. if the master sends a7h, this signifies a software reboot. the send byte procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address or com - mand code. 5) the addressed slave asserts an ack (or nack) on sda. 6) the master sends a stop condition. receive byte the receive byte protocol allows the master device to read the register content of the max16065/max16066 (see figure 14). the flash or register address must be preset with a send byte or write word protocol first. once the read is complete, the internal pointer increases by one. repeating the receive byte protocol reads the contents of the next address. the receive byte procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a read bit (high). 3) the addressed slave asserts an ack on sda. 4) the slave sends 8 data bits. 5 the master asserts a nack on sda. 6) the master generates a stop condition. write byte the write byte protocol (see figure 14) allows the master device to write a single byte in the default page, extended page, or flash page, depending on which page is currently selected. the write byte procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). figure 13. acknowledge scl 1 s 2 89 sda by transmitter sda by receiver clock pulse for acknowledge nack ack downloaded from: http:///
44 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address. 5) the addressed slave asserts an ack on sda. 6) the master sends an 8-bit data byte. 7) the addressed slave asserts an ack on sda. 8) the master sends a stop condition. to write a single byte, only the 8-bit memory address and a single 8-bit data byte are sent. the data byte is written to the addressed location if the memory address is valid. the slave asserts a nack at step 5 if the memory address is not valid.when pec is enabled, the write byte protocol becomes: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends an 8-bit memory address. 5) the active slave asserts an ack on the data line. 6) the master sends an 8-bit data byte. 7) the slave asserts an ack on the data line. 8) the master sends an 8-bit pec byte. 9) the slave asserts an ack on the data line (if pec is good, otherwise nack). 10) the master generates a stop condition. read byte the read byte protocol (see figure 14) allows the master device to read a single byte located in the default page, extended page, or flash page depending on which page is currently selected. the read byte procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address. 5) the addressed slave asserts an ack on sda. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address and a read bit (high). 8) the addressed slave asserts an ack on sda. 9) the slave sends an 8-bit data byte. 10) the master asserts a nack on sda. 11) the master sends a stop condition. if the memory address is not valid, it is nacked by the slave at step 5 and the address pointer is not modified. when pec is enabled, the read byte protocol becomes: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends 8-bit memory address. 5) the active slave asserts an ack on the data line. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave id plus a read bit (high). 8) the addressed slave asserts an ack on the data line. 9) the slave sends 8 data bits. 10) the master asserts an ack on the data line. 11) the slave sends an 8-bit pec byte. 12) the master asserts a nack on the data line. 13) the master generates a stop condition. block write the block write protocol (see figure 14) allows the master device to write a block of data (1 byte to 16 bytes) to memory. preload the destination address by a previous send byte command; otherwise the block write command begins to write at the current address pointer. after the last byte is written, the address pointer remains preset to the next valid address. if the number of bytes to be written causes the address pointer to exceed 8fh for configuration registers or configuration flash or ffh for user flash, the address pointer stays at 8fh or ffh, respectively, overwriting this memory address with the remaining bytes of data. the slave generates a nack at step 5 if the command code is invalid or if the device is busy, and the address pointer is not altered. the block write procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends the 8-bit command code for a block write (a5h). 5) the addressed slave asserts an ack on sda. downloaded from: http:///
45 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 6) the master sends the 8-bit byte count (1 byte to 16 bytes), n. 7) the addressed slave asserts an ack on sda. 8) the master sends 8 bits of data. 9) the addressed slave asserts an ack on sda. 10) repeat steps 8 and 9 n - 1 times. 11) the master sends a stop condition. when pec is enabled, the block write protocol becomes: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends 8 bits of the block write command code. 5) the slave asserts an ack on the data line. 6) the master sends an 8-bit byte count (min 1, max 16), n. 7) the slave asserts an ack on the data line. 8) the master sends 8 bits of data. 9) the slave asserts an ack on the data line. 10) repeat 8 and 9 n - 1 times. 11) the master sends an 8-bit pec byte. 12) the slave asserts an ack on the data line (if pec is good, otherwise nack). 13) the master generates a stop condition. block read the block read protocol (see figure 14) allows the master device to read a block of up to 16 bytes from memory. read fewer than 16 bytes of data by issuing an early stop condition from the master, or by generating a nack with the master. the destination address should be preloaded by a previous send byte command; otherwise the block read command begins to read at the current address pointer. if the number of bytes to be read causes the address pointer to exceed 8fh for the configuration register or configuration flash or ffh in user flash, the address pointer stays at 8fh or ffh, respectively. the block read procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends 8 bits of the block read command (a6h). 5) the slave asserts an ack on sda, unless busy. 6) the master generates a repeated start condition. 7) the master sends the 7-bit slave address and a read bit (high). 8) the slave asserts an ack on sda. 9) the slave sends the 8-bit byte count (16). 10) the master asserts an ack on sda. 11) the slave sends 8 bits of data. 12) the master asserts an ack on sda. 13) repeat steps 11 and 12 up to fifteen times. 14) the master asserts a nack on sda. 15) the master sends a stop condition. when pec is enabled, the block read protocol becomes: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends 8 bits of the block read command code. 5) the slave asserts an ack on the data line unless busy. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave id plus a read bit (high). 8) the slave asserts an ack on the data line. 9) the slave sends an 8-bit byte count (16). 10) the master asserts an ack on the data line. 11) the slave sends 8 bits of data. 12) the master asserts an ack on the data line. 13) repeat 11 and 12 up to 15 times. 14) the slave sends an 8-bit pec byte. 15) the master asserts a nack on the data line. 16) the master generates a stop condition. smbalert the max16065/max16066 support the smbus alert protocol. to enable the smbus alert output, set r35h[1:0] according to table 29, which configures a fault1, fault2, or any_fault output to act as the smbus alert. this output is open-drain and uses the wired-or configura - tion with other devices on the smbus. during a fault, the max16065/max16066 assert alert low, signaling the master that an interrupt has occurred. the master downloaded from: http:///
46 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 responds by sending the ara (alert response address) protocol on the smbus. this protocol is a read byte with 09h as the slave address. the slave acknowledges the ara (09h) address and sends its own smbus address to the master. the slave then deasserts alert . the master can then query the slave and determine the cause of the fault. by checking r1ch[6], the master can confirm that the max16065/max16066 triggered the smbus alert. the master must send the ara before clearing r1ch[6]. clear r1ch[6] by writing a ?1.? jtag serial interface the max16065/max16066 feature a jtag port that complies with a subset of the ieee? 1149.1 specification. either the smbus or the jtag interface can be used to access internal memory; however, only one interface is allowed to run at a time. the max16065/max16066 do not support ieee 1149.1 boundary-scan function - ality. the max16065/max16066 contain extra jtag instructions and registers not included in the jtag specification that provide access to internal memory. the extra instructions include load address, write data, read data, reboot, save. test access port (tap) controller state machine the tap controller is a finite state machine that responds to the logic level at tms on the rising edge of tck. see figure 16 for a diagram of the finite state machine. the possible states are described in the following: test-logic-reset: at power-up, the tap controller is in the test-logic-reset state. the instruction register contains the idcode instruction. all system logic of the device operates normally. this state can be reached from any state by driving tms high for five clock cycles. run-test/idle: the run-test/idle state is used between scan operations or during specific tests. the instruction register and test data registers remain idle. select-dr-scan: all test data registers retain their previ - ous state. with tms low, a rising edge of tck moves the controller into the capture-dr state and initiates a scan sequence. tms high during a rising edge on tck moves the controller to the select-ir-scan state. capture-dr: data can be parallel-loaded into the test data registers selected by the current instruction. if the instruction does not call for a parallel load or the selected test data register does not allow parallel loads, the test data register remains at its current value. on the rising edge of tck, the controller goes to the shift-dr state if tms is low or it goes to the exit1-dr state if tms is high. shift-dr: the test data register selected by the current instruction connects between tdi and tdo and shifts data one stage toward its serial output on each rising edge of tck while tms is low. on the rising edge of tck, the controller goes to the exit1-dr state if tms is high. exit1-dr: while in this state, a rising edge on tck puts the controller in the update-dr state. a rising edge on tck with tms low puts the controller in the pause-dr state. pause-dr: shifting of the test data registers halts while in this state. all test data registers retain their previous state. the controller remains in this state while tms is low. a rising edge on tck with tms high puts the con - troller in the exit2-dr state.exit2-dr: a rising edge on tck with tms high while in this state puts the controller in the update-dr state. a ris - ing edge on tck with tms low enters the shift-dr state.update-dr: a falling edge on tck while in the update- dr state latches the data from the shift register path of the test data registers into a set of output latches. this prevents changes at the parallel output because of changes in the shift register. on the rising edge of tck, the controller goes to the run-test/idle state if tms is low or goes to the select-dr-scan state if tms is high. table 29. smbus alert configuration ieee is a registered service mark of the institute of electrical and electronics engineers, inc. register address flash address bit range description 35h 235h [1:0] smbus alert configuration:00 = disabled 01 = fault1 is smbus alert 10 = fault2 is smbus alert 11 = any_fault is smbus alert downloaded from: http:///
47 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 figure 14. smbus protocols send byte format s address slave address: addressof the slave on the serial interface bus. data byte: presets the internaladdress pointer or represents a command. r/w ack command ack p 7 bits 00 0 8 bits receive byte format s address slave address: addressof the slave on the serial interface bus. data byte: data is read fromthe location pointed to by the internal address pointer. r/w ack data nack p 7 bits 10 01 1 8 bits write byte format s address slave address: addressof the slave on the serial interface bus. command byte:sets the internal address pointer. r/w ack command ack 7 bits 00 0 0 8 bits data byte: data is written tothe locations set by the internal address pointer. data ack p 8 bits read byte format s slave address slave address: addressof the slave on the serial interface bus. command byte:sets the internal address pointer. r/w r/w ack command ack 7 bits 00 00 1 8 bits data byte: data is read fromthe locations set by the internal address pointer. sr r/w r/w slave address r/w 7 bits 1 block write format s address slave address: addressof the slave on the serial interface bus. command byte:a5h data byte: data is written to the locationsset by the internal address pointer. ack command ack 7 bits 0 0 0 00 00 8 bits byte count = n ack p 8 bits data byte 1 ack 8 bits data byte n ack 8 bits data byte ? ack ack data byte 8 bits 8 bits smbalert# alert response address:only the device that interrupted the master responds to this address. slave address: slave placesits own address on the serial bus. s address r/w ack data nack p 0001100 d.c. 8 bits nack p slave to mastermaster to slave block read format s address slave address: addressof the slave on the serial interface bus. s = start conditionp = stop condition sr = repeated start condition d.c. = don?t care ack = acknowledge, sda pulled low during rising edge of scl.nack = not acknowledge, sda left high during rising edge of scl. all data is clocked in/out of the device on rising edges of scl. = sda transitions from high to low during period of scl.= sda transitions from low to high during period of scl. command byte:a6h data byte: data is read from the locationsset by the internal address pointer. ack command ack 7 bits address slave address: addressof the slave on the serial interface bus. 7 bits 00 0 00 0 0 1 8 bits ack p 8 bits data byte 1 ack 8 bits ack data byte n 8 bits data byte ? nack 8 bits sr ack 1 byte count = n s address command pec p 7 bits 0 0 8 bits 0 write byte format with pec read byte format with pec block write with pec block read with pec data 0 8 bits 0 8 bits s s s address command data pec p p sr sr address 0 0 0 1 0 0 0 00 0 00 nack 1 p 0 0 0 8 bits 0 00 8 bits command 8 bits command 8 bits 0 0 0 8 bits data byte n 8 bits data byte n 8 bits pec 8 bits pec 8 bits 1 7 bits address 7 bits address 7 bits 10 7 bits byte count n 8 bits byte count n 8 bits address 7 bits data byte 1 8 bits data byte 1 8 bits data byte 8 bits data byte 8 bits r/w r/w r/w r/w r/w r/w ac ka c ka c ka ck ac ka c ka ck nack ack ac ka c ka c ka c ka c ka ck ac ka c ka c ka c ka c ka c ka ck ack downloaded from: http:///
48 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 select-ir-scan: all test data registers retain the previ - ous states. the instruction register remains unchanged during this state. with tms low, a rising edge on tck moves the controller into the capture-ir state. tms high during a rising edge on tck puts the controller back into the test-logic-reset state. capture-ir: use the capture-ir state to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of tck. if tms is high on the rising edge of tck, the controller enters the exit1-ir state. if tms is low on the rising edge of tck, the controller enters the shift-ir state. shift-ir: in this state, the shift register in the instruction register connects between tdi and tdo and shifts data one stage for every rising edge of tck toward the tdo serial output while tms is low. the parallel outputs of the instruction register as well as all test data registers remain at the previous states. a rising edge on tck with tms high moves the controller to the exit1-ir state. a rising edge on tck with tms low keeps the controller in the shift-ir state while moving data one stage through the instruction shift register. figure 15. jtag block diagram test access port (tap) controller instruction register [length = 5 bits] bypass register [length = 1 bit] identification register [length = 32 bits] user code register [length = 32 bits] memory address register [length = 8 bits] memory read register [length = 8 bits] memory write register [length = 8 bits] 11111 00000 00011 00100 00101 00110 00111 mux 2 tdo tdi tms tck 01000 registers and flash 01001 01010 01011 01100 mux 1 00111 01000 01100 01011 01010 01001 reboot save setusrflsh rstflshadd rstusrflsh setflshadd command decoder r pu v db downloaded from: http:///
49 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 exit1-ir: a rising edge on tck with tms low puts the controller in the pause-ir state. if tms is high on the rising edge of tck, the controller enters the update-ir state. pause-ir: shifting of the instruction shift register halts temporarily. with tms high, a rising edge on tck puts the controller in the exit2-ir state. the controller remains in the pause-ir state if tms is low during a rising edge on tck. exit2-ir: a rising edge on tck with tms high puts the controller in the update-ir state. the controller loops back to shift-ir if tms is low during a rising edge of tck in this state. update-ir: the instruction code that has been shifted into the instruction shift register latches to the parallel outputs of the instruction register on the falling edge of tck as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on tck with tms low puts the controller in the run- test/idle state. with tms high, the controller enters the select-dr-scan state. instruction register the instruction register contains a shift register as well as a latched 5-bit wide parallel output. when the tap controller enters the shift-ir state, the instruction shift register connects between tdi and tdo. while in the shift-ir state, a rising edge on tck with tms low shifts the data one stage toward the serial output at tdo. a rising edge on tck in the exit1-ir state or the exit2-ir state with tms high moves the controller to the update- ir state. the falling edge of that same tck latches the data in the instruction shift register to the instruction register parallel output. table 30 shows the instructions supported by the max16065/max16066 and the respective operational binary codes.bypass: when the bypass instruction is latched into the instruction register, tdi connects to tdo through the 1-bit bypass test data register. this allows data to pass from tdi to tdo without affecting the device?s operation. idcode: when the idcode instruction is latched into the parallel instruction register, the identification data register is selected. the device identification code is loaded into the identification data register on the rising edge of tck following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially through tdo. during test-logic-reset, the idcode instruction is forced into the instruction register. the iden - tification code always has a ?1? in the lsb position. the next 11 bits identify the manufacturer?s jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. see table 31. usercode: when the usercode instruction latches into the parallel instruction register, the user-code data register is selected. the device user-code loads into the user-code data register on the rising edge of tck fol - lowing entry into the capture-dr state. shift-dr can be used to shift the user-code out serially through tdo. see table 32. this instruction can be used to help identify multiple max16065/max16066 devices connected in a jtag chain. load address: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the max16065/max16066. when the load address instruction latches into the instruction register, tdi connects to tdo through the 8-bit memory address test data register during the shift-dr state. read data: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the max16065/max16066. when the read data instruction latches into the instruction register, tdi con - nects to tdo through the 8-bit memory read test data register during the shift-dr state. write data: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the max16065/max16066. when the write data instruction latches into the instruction register, tdi con - nects to tdo through the 8-bit memory write test data register during the shift-dr state. reboot: this is an extension to the standard ieee 1149.1 instruction set to initiate a software-controlled reset to the max16065/max16066. when the reboot instruction latches into the instruction register, the max16065/max16066 resets and immediately begins the boot-up sequence. save: this is an extension to the standard ieee 1149.1 instruction set that triggers a fault log. the current adc conversion results along with fault information are saved to flash depending on the configuration of the critical fault log control register (r6dh). setflshadd: this is an extension to the standard ieee 1149.1 instruction set that allows access to the flash page. flash registers include adc conversion results and gpio_ input/output data. use this page to access registers 200h to 2ffh rstflshadd: this is an extension to the standard ieee 1149.1 instruction set. use rstflshadd to return to the default page and disable access to the flash page. downloaded from: http:///
50 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 figure 16. tap controller state diagram table 30. jtag instruction set table 31. 32-bit identification code test-logic-reset 1 1 11 0 0 run-test/idle 0 0 0 01 1 1 0 0 10 11 0 1 0 1 select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 0 0 0 01 1 01 1 instruction code notes bypass 0x1f mandatory instruction code idcode 0x00 load manufacturer id code/part number usercode 0x03 load user code load address 0x04 load address register content read data 0x05 read data pointed by current address write data 0x06 write data pointed by current address reboot 0x07 reboot flash data content into register file save 0x08 trigger emergency save to flash setflshadd 0x09 flash page access on rstflshadd 0x0a flash page access off setusrflsh 0x0b user flash access on (must be in flash page already) rstusrflsh 0x0c user flash access off (return to flash page) msb lsb version (4 bits) part number (16 bits) manufacturer (11 bits) fixed value (1 bit) 0001 1000000000000001 00011001011 1 downloaded from: http:///
51 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 setusrflsh: this is an extension to the standard ieee 1149.1 instruction set that allows access to the user flash page. when on the configuration flash page, send the setusrflsh command, all addresses are recognized as flash addresses only. use this page to access regis - ters 300h to 3ffh.rstusrflsh: this is an extension to the standard ieee 1149.1 instruction set. use rstusrflsh to return to the configuration flash page and disable access to the user flash. restrictions when writing to flash flash must be written to 8 bytes at a time. the initial address must be aligned to 8-byte boundaries?the 3 lsbs of the initial address must be ?000?. write the 8 bytes using eight successive write data commands. applications information unprogrammed device behavior when the flash has not been programmed using the jtag or smbus interface, the default configuration of the en_out_ outputs is open-drain active-low. this means that the en_out_ outputs are high impedance. when it is necessary to hold an en_out_ high or low to prevent premature startup of a power supply before the flash is programmed, connect a resistor from en_out_ to ground or the supply voltage. avoid connecting a resistor to ground when the output is to be configured as open-drain with a separate pullup resistor. device behavior at power-up when v cc is ramped from 0, the reset output is high impedance until v cc reaches 1.4v, at which point reset goes low. all other outputs are high impedance until v cc reaches 2.7v, when the flash contents are copied into register memory. this takes 150 f s (max), after which the outputs assume their programmed states. programming the max16065/max16066 in circuit the max16065/max16066 can be programmed in the application circuit by taking into account the following points during circuit design: u the max16065/max16066 needs to be powered from an intermediate voltage bus or auxiliary voltage sup - ply so programming can occur even when the board?s power supplies are off. this could also be achieved by using oring diodes so that power can be provided through the programming connector. u the smbus or jtag bus lines should not connect through a bus multiplexer powered from a voltage rail controlled by the max16065/max16066. if the device needs to be controlled by an on-board f p, consider connecting the f p to one bus (such as smbus) and use the other bus for in-circuit programming. u an unprogrammed max16065/max16066?s en_out_s go high impedance. ensure that this does not cause undesired circuit behavior. if necessary, connect pull - down resistors to prevent power supplies from turning on. maintaining power during a fault condition power to the max16065/max16066 must be maintained for a specific period of time to ensure a successful flash fault log operation during a fault that removes power to the circuit. table 33 shows the amount of time required depends on the settings in the fault control register (r6dh[1:0]). maintain power for shutdown during fault conditions in applications where the always-on power supply cannot be relied upon by placing a diode and a large capacitor between the voltage source, v in , and v cc (figure 17). the capacitor value depends on v in and the time delay required, t fault_save . use the following formula to cal - culate the capacitor size:c = (t fault_save x i cc(max) )/(v in - v diode - v uvlo ) where the capacitance is in farads and t fault_save is in seconds, i cc(max) is 14ma, v diode is the voltage drop across the diode, and v uvlo is 2.7v. for example, with a v in of 14v, a diode drop of 0.7v, and a t fault_save of 153ms, the minimum required capacitance is 202 f f. table 32. 32-bit user-code data msb lsb don?t care smbus slave id user id (r8ah[7:0]) 00000000000000000 see table 27 downloaded from: http:///
52 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 driving high-side mosfet switches up to eight of the programmable outputs (en_out1? en_out8) of the max16065/max16066 can be configured as charge-pump outputs to drive the gates of series-pass n-channel mosfets. when driving mosfets, these outputs act as simple power switches to turn on the voltage supply rails. approximate the slew rate, sr, using the following formula: sr = i cp /(c gate + c ext ) where i cp is the 4 f a (typ) charge-pump source current, c gate is the gate capacitance of the mosfet, and c ext is the capacitance connected from the gate to ground. if more than eight series-pass mosfets are required for an application, additional series-pass p-channel mosfets can be connected to outputs configured as active-low open drain (figure 18). connect a pullup resistor from the gate to the source of the mosfet, and ensure the absolute maximum ratings of the max16065/ max16066 are not exceeded. configuring the device an evaluation kit and a graphical user interface (gui) is available to create a custom configuration for the device. refer to the max16065/max16066 evaluation kit for configuration. cascading multiple max16065/max16066s multiple max16065/max16066s can be cascaded to increase the number of rails controlled for sequencing and monitoring. there are many ways to cascade the devices depending on the desired behavior. in general, there are several techniques: u configure a gpio_ on each device to be extfault (open drain). externally wire them together with a single pullup resistor. set register bits r72h[5] and r6dh[2] to ?1? so that all faults will propagate between devices. if a critical fault occurs on one device, extfault will assert, triggering the nonvolatile fault logger in all cascaded devices and recording a snap - shot of all system voltages. u connect open-drain reset outputs together to obtain a master system reset signal. u connect all en inputs together for a master enable sig - nal. since the internal timings of each cascaded device are not synchronized, en_out_s placed in the same slot on different devices will not come up in the desired order even if the sequence delays are identical. u consider using an external f p to control the en inputs or the software enable bits of cascaded devices, monitoring the reset outputs as a power-good signal. u for a large number of voltage rails, the max16065/max16066s can be cascaded hierarchically by using one master device?s en_out_s to control the en inputs of several slave devices. table 33. maximum write time figure 17. power circuit for shutdown during fault conditions figure 18. connection for a p-channel series-pass mosfet r6dh[1:0] value description maximum write time (ms) 00 save flags and adc readings 244 01 save flags 77 10 save adc readings 153 11 do not save anything ? max16065max16066 v cc c v in gnd max16065max16066 v out r mon_ en_out_ v in downloaded from: http:///
53 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 controlling power supplies without using the sequencer a f p may control power supplies manually without involving the sequencing slot system by controlling en_out_s configured as gpio_. the output of a power supply controlled this way can be monitored using a mon_ input configured as ?monitoring only(primary sequence)? or ?monitoring only(secondary sequence)? (see the monitoring inputs while sequencing section). to monitor the supply for critical faults, the f p will need to manually set the critical fault enable bit in r6eh to r72h after turning on the en_out_, and manually clear the critical fault enable bit before turning off the en_out_. monitoring current using the differential inputs the max16065/max16066 can monitor up to seven currents using the dedicated current-sense amplifier as well as up to six pairs of inputs configured in differential mode. the accuracy of the differential pairs is limited by the voltage range and the 10-bit conversions. each input pair uses an odd-numbered mon_ input in combination with an even-numbered mon_ input to monitor both the voltage from the odd-numbered mon_ to ground and the voltage difference between the two mon_ inputs. this way a single pair of inputs can monitor the voltage and the current of a power-supply rail. the overvoltage threshold on the even-numbered mon_ inputs can be used as an overcurrent flag. figure 19. graphical user interface screenshot downloaded from: http:///
54 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 figure 20 shows how to connect a current-sense resistor to a pair of mon_ inputs for monitoring both current and voltage. for best accuracy, set the voltage range on the even- numbered mon_ to 1.4v. since the adc conversion results are 10 bits, the monitoring precision is 1.4v/1024 = 1.4mv. for more accurate current measurements, use larger current-sense resistors. the application require - ments should determine the balance between accuracy and voltage drop across the current-sense resistor. layout and bypassing bypass dbp and abp each with a 1 f f ceramic capacitor to gnd. bypass v cc with a 10 f f capacitor to ground. avoid routing digital return currents through a sensitive analog area, such as an analog supply input return path or abp?s bypass capacitor ground connection. use dedicated analog and digital ground planes. connect the capacitors as close as possible to the device. figure 20. current monitoring connection max16065max16066 i load mon odd mon even r s power supply downloaded from: http:///
55 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 register map flash address register address read/ write description adc values, fault registers, gpio_s as input ports?not in flash ? 000 r mon1 adc output, msbs ? 001 r mon1 adc output, lsbs ? 002 r mon2 adc output, msbs ? 003 r mon2 adc output, lsbs ? 004 r mon3 adc output, msbs ? 005 r mon3 adc output, lsbs ? 006 r mon4 adc output, msbs ? 007 r mon4 adc output, lsbs ? 008 r mon5 adc output, msbs ? 009 r mon5 adc output, lsbs ? 00a r mon6 adc output, msbs ? 00b r mon6 adc output, lsbs ? 00c r mon7 adc output, msbs ? 00d r mon7 adc output, lsbs ? 00e r mon8 adc output, msbs ? 00f r mon8 adc output, lsbs ? 010 r mon9 adc output, msbs ? 011 r mon9 adc output, lsbs ? 012 r mon10 adc output, msbs ? 013 r mon10 adc output, lsbs ? 014 r mon11 adc output, msbs ? 015 r mon11 adc output, lsbs ? 016 r mon12 adc output, msbs ? 017 r mon12 adc output, lsbs ? 018 r current-sense adc output ? 019 r csp adc output, msbs ? 01a r csp adc output, lsbs ? 01b r/w fault register?failed line flags ? 01c r/w fault register?failed line flags/overcurrent ? 01d r failing slot during secondary sequence ? 01e r gpio data in (read only) ? 01f r en_out_ as gpio data in (read only) ? 020 r/w flash status/reset output monitor ? 021 r current state of the fsm downloaded from: http:///
56 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 register map (continued) flash address register address read/ write description gpio and output dependencies/configurations 230 030 r/w out configuration 231 031 r/w out configuration 232 032 r/w out configuration 233 033 r/w charge-pump configuration, bits 234 034 r/w en_out_ as gpio data out 235 035 r/w smbalert pin configuration 236 036 r/w fault1 dependencies 237 037 r/w fault1 dependencies 238 038 r/w fault2 dependencies 239 039 r/w fault2 dependencies 23a 03a r/w fault1/fault2 secondary overcurrent dependencies 23b 03b r/w reset output configuration 23c 03c r/w reset output dependencies 23d 03d r/w reset output dependencies 23e 03e r/w gpio data out 23f 03f r/w gpio configuration 240 040 r/w gpio configuration 241 041 r/w gpio configuration 242 042 r/w gpio push-pull/open drain adc?conversions 243 043 r/w adcs voltage ranges?mon_ monitoring 244 044 r/w adcs voltage ranges?mon_ monitoring 245 045 r/w adcs voltage ranges?mon_ monitoring 246 046 r/w differential pairs enables 247 047 r/w current-sense gain-setting (csp, hv, or lv) input thresholds 248 048 r/w mon1 secondary selectable uv/ov 249 049 r/w mon1 primary ov 24a 04a r/w mon1 primary uv 24b 04b r/w mon2 secondary selectable uv/ov 24c 04c r/w mon2 primary ov 24d 04d r/w mon2 primary uv 24e 04e r/w mon3 secondary selectable uv/ov 24f 04f r/w mon3 primary ov 250 050 r/w mon3 primary uv 251 051 r/w mon4 secondary selectable uv/ov 252 052 r/w mon4 primary ov 253 053 r/w mon4 primary uv 254 054 r/w mon5 secondary selectable uv/ov 255 055 r/w mon5 primary ov downloaded from: http:///
57 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 register map (continued) flash address register address read/ write description 256 056 r/w mon5 primary uv 257 057 r/w mon6 secondary selectable uv/ov 258 058 r/w mon6 primary ov 259 059 r/w mon6 primary uv 25a 05a r/w mon7 secondary selectable uv/ov 25b 05b r/w mon7 primary ov 25c 05c r/w mon7 primary uv 25d 05d r/w mon8 secondary selectable uv/ov 25e 05e r/w mon8 primary ov 25f 05f r/w mon8 primary uv 260 060 r/w mon9 secondary selectable uv/ov 261 061 r/w mon9 primary ov 262 062 r/w mon9 primary uv 263 063 r/w mon10 secondary selectable uv/ov 264 064 r/w mon10 primary ov 265 065 r/w mon10 primary uv 266 066 r/w mon11 secondary selectable uv/ov 267 067 r/w mon11 primary ov 268 068 r/w mon11 primary uv 269 069 r/w mon12 secondary selectable uv/ov 26a 06a r/w mon12 primary ov 26b 06b r/w mon12 primary uv 26c 06c r/w secondary overcurrent threshold fault setup 26d 06d r/w save after extfault fault control 26e 06e r/w faults causing store in flash 26f 06f r/w faults causing store in flash 270 070 r/w faults causing store in flash 271 071 r/w faults causing store in flash 272 072 r/w faults causing store in flash timeouts 273 073 r/w overcurrent debounce, watchdog mode, secondary threshold type, software enables 274 074 r/w adc fault deglitch/autoretry configuration 275 075 r/w wdi toggle, power-up fault timer, reverse sequence 276 076 r/w watchdog reset output enable, watchdog timers 277 077 r/w sequence delay for slot 0 and slot 1 278 078 r/w sequence delay for slot 2 and slot 3 279 079 r/w sequence delay for slot 4 and slot 5 27a 07a r/w sequence delay for slot 6 and slot 7 downloaded from: http:///
58 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 register map (continued) flash address register address read/ write description 27b 07b r/w sequence delay for slot 8 and slot 9 27c 07c r/w sequence delay for slot 10 and slot 11 27d 07d r/w primary sequence final slot, sequence delay for slot 12 miscellaneous 27e 07e r/w mon1/mon2 slot assignment 27f 07f r/w mon3/mon4 slot assignment 280 080 r/w mon5/mon6 slot assignment 281 081 r/w mon7/mon8 slot assignment 282 082 r/w mon9/mon10 slot assignment 283 083 r/w mon11/mon12 slot assignment 284 084 r/w en_out1/en_out2 slot assignment 285 085 r/w en_out3/en_out4 slot assignment 286 086 r/w en_out5/en_out6 slot assignment 287 087 r/w en_out7/en_out8 slot assignment 288 088 r/w en_out9/en_out10 slot assignment 289 089 r/w en_out11/en_out12 slot assignment 28a 08a r/w customer use (version) 28b 08b r/w pec enable/smbus address 28c 08c r/w lock bits 28d 08d r revision code nonvolatile fault log 200 ? r/w sequence state 201 ? r/w fault flags, mon1?mon8 202 ? r/w fault flags, mon9?mon12, oc, extfault 203 ? r/w mon1 adc output 204 ? r/w mon2 adc output 205 ? r/w mon3 adc output 206 ? r/w mon4 adc output 207 ? r/w mon5 adc output 208 ? r/w mon6 adc output 209 ? r/w mon7 adc output 20a ? r/w mon8 adc output 20b ? r/w mon9 adc output 20c ? r/w mon10 adc output 20d ? r/w mon11adc output 20e ? r/w mon12 adc output 20f ? r/w current-sense adc output user flash 300 39f r/w user flash 3a0 3af ? reserved 3b0 3ff r/w user flash downloaded from: http:///
59 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 typical operating circuits max16065max16066 +3.3v v supply c scl mon2?mon11 v cc mon1 sda reset fault resetint wdi wdo i/oint ao gnd dc-dc gnd in out dc-dc gnd in out dc-dc gnd in out mon12 downloaded from: http:///
60 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 typical operating circuits (continued) max16065max16066 +3.3v v supply c scl mon odd v cc mon1 mon2 sda reset fault resetint wdi wdo i/oint ao gnd dc-dc gnd in out dc-dc gnd in note: mon odd = mon1, mon3, mon5, mon7, mon9, mon11 mon even = mon2, mon4, mon6, mon8, mon10, mon12 out dc-dc gnd in out mon11 load load load mon even mon12 downloaded from: http:///
61 maxim integrated 12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 chip information process: bicmos package information for the latest package outline information and land patterns, (footprints) go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 48 tqfn-ep t4877+6 21-0144 90-0132 40 tqfn-ep t4066+5 21-0141 90-0055 downloaded from: http:///
12-channel/8-channel, flash-configurable system managers with nonvolatile fault registers max16065/max16066 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 62 maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2015 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/09 initial release ? 1 2/11 made correction to tables 6 and 23 16, 36 2 8/11 revised electrical characteristics , detailed description , and figure 3 2, 4, 11, 15 3 11/14 corrected dbp, abp to gnd row in absolute maximum ratings 2 4 3/15 removed mon9/mon10, mon11/mon12 in the voltage/current monitoring section and bit range [4] and [5] in table 9; moved pin configurations to page 9 18, 21, 60 downloaded from: http:///

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